[gem5-users] Re: Issue with strange virtual address access

Hi Jason, Thank you very much for your swift response. I hugely appreciate it. Wishing you a great day. Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: Issue with strange virtual address access

Hi Tom, I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags which may help figure it out. It's possible that's the address of a dynamically-loaded library as well. Also, this trace looks like it came from Arm instead of x86. I don't have as much experience looking at Arm

[gem5-users] Re: Huge pages with ARM

Hi! Thanks for the quick response. I am indeed using SE mode. If I use FS mode, do I have to recompile the guest kernel in order to change the page size? Kind regards, João Vieira - ECE PhD Student and RA at INESC-ID, Instituto Superior Técnico, University of Lisbon, Portugal

[gem5-users] Re: Issue with strange virtual address access

Hi Jason, I have one doubt. The following is some selected parts of Exec trace: If we look at lines: line 4: ldr x1, [sp]: MemRead : D=0x0001 A=0x7efe70 line 74 : ldr x1, [x0]: MemRead : D=0x0010 A=0x7efe90 line 88 :

[gem5-users] Re: Huge pages with ARM

Hi, Are you running FS or SE simulations? In FS it is configurable through the guest kernel, in SE mode we use 4K by default (see src/arch/arm/page_size.hh) You might try to change the hardcoded value in the page_size.hh file though this has never been tested and it might not work without some

[gem5-users] Re: Building Old gem5 error

Hello Abdelrahman, Unfortunately, it's incredibly difficult to keep the development environment for older versions of gem5 working. You may be able to find an old dockerfile in those gem5 repositories that could help to recreate the build environment. (I'm not sure if we were using docker at the

[gem5-users] Re: Issue with strange virtual address access

Hi Liyan, This looks like a stack address to me, so it won't appear in the objdump. Since you're using SE mode, gem5 is controlling the physical address mappings (not the OS). You can use the "Vma" debug flag to see all of the virtual memory areas that gem5 creates/assigns. the "SyscallVerbose"

[gem5-users] Huge pages with ARM

Hi, I am trying to use Huge pages (as big as 1GB) in gem5, but there seems to be little to none documentation about the subject. Does anyone know how to change the page size? I am using the ARM ISA, in case it matters. Thanks in advance! Kind regards -- Joao Vieira ECE PhD Student at

[gem5-users] Re: ARM model - load instruction reads non-zero data from an address which was not written out prior (as per traces)

Hi , I have attached a shorter Exec trace to this message. If we look at lines: line 4: ldr x1, [sp]: MemRead : D=0x0001 A=0x7efe70 line 74 : ldr x1, [x0]: MemRead : D=0x0010 A=0x7efe90 line 88 : ldr x3, [x8,

[gem5-users] SimpleMemobj in FS simulation?

Hello everyone. Recently I've been trying to create a new memory object to run in FS simulation. For it i use the SimpleMemobj (https://www.gem5.org/documentation/learning_gem5/part2/memoryobject/) code as a template. During FS tests, I've run into a lot of troubles causing the simulation

[gem5-users] Building Old gem5 error

Hello, I am trying to build older version(s) of gem5 (specifically, the ones used for InvisiSpec and STT). I understand that this version of gem5 requires python2, thus, I build a virtual environment based on python2 and re-installed scons. However, when I run this command: scons

[gem5-users] Failed to run tlm-gem5 cosimualtion examples in util/tlm

Hi, I am working on combine external sc_models to Gem5. So I try to follow the tlm tutorial in gem5/util/tlm/README. Following the building steps in the REDME file, there is no issue on the first two line and end with normal gem5.opt output: >cd ../../ >/usr/bin/env python3 `which scons`

[gem5-users] completeAcc not defined! (adding new pseudo instruction to X86 arch)

Hello everyone, I am new to gem5. Due to my project, I should add a new pseudo instruction to X85 architecture to add more functions for the main memory. However, when I run the simulation in timing mode, I encountered the error as below: panic: completeAcc not defined! It means I have to

[gem5-users] Problem with prefetcher configuration in 03_ARM_v7a.py

Hello all, I want to figure out the effects of prefetchers on CPU performance. So I run gem5 in SE mode and choose O3_ARM_v7a as the CPU type. I config the stride prefetcher in l2cache in the CPU configuration script named O3_ARM_v7a.py. The problem is that the prefetcher is only enabled when

[gem5-users] Re: x86 instructions with microops

Hi Tariq Azmy, Were you able to get more information on the original question that you had asked? Especially the file which has the list of all supported microops per arch? Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe