[gem5-users] Custom instructions connecting to C++ library

Hey folks, I've been working on custom instructions for RISC-V within Gem5 and am able to manage basic logic. However, I'd like to implement a custom component that interfaces with these new instructions and I'm having trouble figuring out where to start. The custom instructions doc

[gem5-users] How to port designs simulated on gem5 to real time FPGAs

Hi all , I am curious to know how to port a design made on gem5 on to a FPGA board , there is a bit of gap in my mind on the steps that i would want to follow,i found a paper in this line which shows the following steps [image: Screenshot from 2023-06-29 15-03-31.png] paper: https://carrv.github.

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

Thanks for the update. On Thu, Jun 29, 2023, 10:08 PM Jason Lowe-Power wrote: > Full system mode is fully supported for RISC-V. There should not be any > problems with running pthreads on RISC-V. > > (Side note: There could be a small bug in the RISC-V atomic > instructions... we're looking into

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

Full system mode is fully supported for RISC-V. There should not be any problems with running pthreads on RISC-V. (Side note: There could be a small bug in the RISC-V atomic instructions... we're looking into it, but haven't been able to track it down.) Cheers, Jason On Thu, Jun 29, 2023 at 4:05

[gem5-users] Re: [EXT] Re: Running benchmarks and gem5art

Nick, Thank you for the links, I will try them and let you know. It looks like exactly what I was looking for. Nick From: Nick Felker Sent: Thursday, June 29, 2023 11:07 AM To: The gem5 Users mailing list Cc: Beser, Nicholas D. Subject: [EXT] Re: [gem5-users] Running benchmarks and gem5art

[gem5-users] Create Uncacheable Memory

I would like to create a region of memory that is not cacheable, and have this memory accessible from a user-space program. I want to test the performance effects of using memory that is cacheable vs. memory that is not. Can this be done in SE mode? Or would this kind of a thing require FS mode?

[gem5-users] Re: Running benchmarks and gem5art

I managed to run STREAM and Whetstone/Dhrystone https://fleker.medium.com/running-and-evaluating-stream-benchmark-for-nvm-in-gem5-3dd07ae9ccaa https://fleker.medium.com/building-running-whetstone-dhrystone-in-gem5-90d465a10bb4 As you had mentioned, some of them are proprietary and that made it h

[gem5-users] Running benchmarks and gem5art

I have been preparing a lecture for my computer architecture class on running benchmarks using gem5. I noticed when I searched the web for examples, gem5art came up. I had been using the bootcamp 2022 tutorial as a guideline, so I am not sure where gem5art fits in. (https://www.gem5.org/documen

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

Thanks for the reply. On Thu, Jun 29, 2023, 2:11 PM Víctor Soria wrote: > Hi Srikanta, > > In the past, I've been able to run pthreads mutex with ruby using Arm > and FS mode. By default, pthreads use syscalls to the OS to sleep or > wake up threads. As far as I know, FS does not work with RISCV

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

Hi Srikanta, In the past, I've been able to run pthreads mutex with ruby using Arm and FS mode. By default, pthreads use syscalls to the OS to sleep or wake up threads. As far as I know, FS does not work with RISCV. Therefore, you could try to select the pthread mutex type to spinlock to avoi

[gem5-users] Hi does gem5 Ruby support pthreads lock and unlock

Hi , I am running pthreads matmul program for riscv in se mode , but with lock and unlock instructions I am getting read error in Ruby .. Do i have to compile with mthreads .. Thanks Chaitanya ___ gem5-users mailing list -- gem5-users@gem5.org To unsubsc