[gem5-users] Re: Gem5 SE mode with SystemC for RISC-V

2023-08-04 Thread siva sankar via gem5-users
Hi Zitai, In config_mem() in configs/common/MemConfig.py, commenting out the following worked for me: if opt_tlm_memory:system.external_memory = m5.objects.ExternalSlave(port_type="tlm_slave", port_data=opt_tlm_memory, port=system.membus.mem_side_ports,

[gem5-users] Re: Gem5 SE mode with SystemC for RISC-V

2023-08-04 Thread Harshil Patel via gem5-users
Hi Zitai, Here are some examples of using SystemC with gem5: https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.py https://github.com/gem5/gem5/tree/develop/util/tlm However, it should be noted that the integration of SystemC with gem5 is not being actively maintained by the

[gem5-users] Re: RISCV Vector Extension in gem5

2023-08-04 Thread Jason Lowe-Power via gem5-users
Hello, No, we don't have any explicit documentation on this. I think that the fault-only-first are the few instructions that are not implemented. Cheers, Jason On Thu, Aug 3, 2023 at 10:25 PM X BJ wrote: > Hello, > > Thank you very much, it is exactly what I need ! > > BTW, is there a

[gem5-users] Gem5 SE mode with SystemC for RISC-V

2023-08-04 Thread 泰。 via gem5-users
Hello All, I have been searching for a demonstration or example that showcases the integration of Gem5 SE mode with SystemC for the RISC-V architecture. I am a beginner in Gem5, and I am trying to connect using the following method, but I am facing an 'AttributeError: Class StubWorkload has