[gem5-users] Re: BasicPioDevice read() / write() not responding

Hello everyone, I'm hitting the exact same problem on ARM as Andreas. I have a physical address mapped into the virtual address space and marked it as uncacheable. When I now write to the virtual address from my SE-program (multiple times), exactly one read access is made to the corresponding

[gem5-users] Re: Squashing Instructions after Page Table Fault

I have used more debug flags, which increased the execution time by a lot, but I got some new information out of it:   Addresses : var = 39b765b0, start = 198325b0, phys = 198325b0 (output in meltdown "reliability.c" code, after line 39)   O3CPU: Ticking main, O3CPU. 15059411234500: system.re

[gem5-users] Issuing random instructions from readyInsts

Hi all, I'm currently working on the O3 CPU model and want to issue random instructions in the IWE stage during the readyInsts issuing. It seems like the program forbids such actions and asserts that the instruction being issued is the oldest one. Am I looking in the wrong place to do this? Any he