Hi,
Usually in SE mode, the page would be pre-allocated when the ELF file(what's
also called image download by me previously) is initiated/downloaded to the
memory. The allocated page can be checked when enabling MMU debug-flag.
I would suggest you to check the error address to confirm whe
Hi:
First of all, I am very, very grateful to Hao Nguyen, who answered me
another question about full system simulation the other day, because I
don't know much about gem5 user lists, and clicking on the reply below
always shows a connection error, so I haven't been able to reply.
I still w
Thank you for your help! It really work!!!
On Fri, Jan 12, 2024 at 4:47 PM Hoa Nguyen wrote:
> Hi,
>
> The problem seems to be that the gem5 simulation and the m5term call are
> run on different virtual machines.
>
> If you're using docker then please make sure that you're calling m5term on
> th
Hi Nazmus
On 15/01/2024 14:32, Nazmus Sakib wrote:
Hello. Thanks for your response.
I am running O3 cpu (ARMO3CPU), not minor.
It's the same:
https://github.com/gem5/gem5/blob/stable/src/cpu/o3/lsq.cc#L816
Also, I get it that LSQ unit can do this.
But a cache must have separate logic for sc
Hello. Thanks for your response.
I am running O3 cpu (ARMO3CPU), not minor.
Also, I get it that LSQ unit can do this.
But a cache must have separate logic for scalar and vector read/writes, as
scheduling events to support a timing model for vector load/store must be
different ?
Also, the intercon
Hi Nazmus,
On 15/01/2024 02:41, Nazmus Sakib wrote:
Thank you. I will try to switch to starter_se.py.
I still had some questions regarding SVE.
1. When I compile with msve-vector-bit set to 512, I can see PTRUE instruction,
which is replaced by whilelow when I compile without setting the vector
