[gem5-users] Can the packet check the CPU that will arrive?

I want to check which CPU core a particular packet arrives at in a multi-core system. Is there any way to check the packet data? Or should I look at the other part? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to

[gem5-users] Where modified this gem5 code for checking cpu's number in multiprocess and tracing packet in SE module?

Hello gem5 users everyone i would like to know how the benchmark of SPLASH2 communicates between CPU and dCache in a multi-core environment through Gem5. Through this link, http://learning.gem5.org/book/part2/memoryobject.html, I was able to confirm that communication between CPU and dcache is

[gem5-users] Where does gem5 decode and how to compute packet on the cpu?

I'm success tracking data movement between L1DCache and CPU with your help. Therefore i get packet between L1DCache and CPU. So i want to find packet decoding location source code and how to compute packet on the cpu.. ___ gem5-users mailing list --

[gem5-users] How to Changed Commmonitor output?

if Commmonitor exist between L1D cache and CPU, output is Packet information encoding protobuf. Output file Packet Information is this link https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU . By changing commmonitor, I would also like to see information about the data contained

[gem5-users] How can identify bits transmitted over Data Bus between L1D Cache and CPU?

With the help of many people on gem5-users, the traffic between the CPU and the L1DCache could be observed using Commmonitor. But i'm trying to find real data transmitting bits between L1D cache and CPU. Sadly, the size of the data transmitted by Commonitor could be determined, but not observed

Re: [gem5-users] how to interpret Commonitor output?

e found here: > https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU > > Serhat > > -- > *From:* gem5-users [gem5-users-boun...@gem5.org] on behalf of DaHoon Park > [pdh930...@gmail.com] > *Sent:* 16 March 2020 02:24 > *To:* gem

[gem5-users] how to interpret Commonitor output?

I want to trace Data Movement between CPU and L1DCache, so i attached Commmonitor of changing BaseCPU.py. Changed Code is this. def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): self.monitor = CommMonitor() self.monitor.trace =

[gem5-users] how to decode commmonitor output?

I changed BaseCPU.py to trace Data Movemnet CPU and L1DCache. Changed Code is this. def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): self.monitor = commMonitor.CommMonitor() self.monitor.trace = memtraceprobe.MemTraceProbe(trace_file="se_trace.ptrc.gz")

Re: [gem5-users] Question about Data bus

Thank you for your reply, I will try that! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Question about Data bus

I want to simulate for observe Data bus traffic in gem5 Is it possible to obtain information about the data actually transmitted in the data bus between cpu and l1dcache by analyzing the packet in gem5? ___ gem5-users mailing list gem5-users@gem5.org

[gem5-users] How to simulate the bus invert method between L2cache to L1D Cache ?

I want to simulate the bus invert method between L2cache to L1D Cache. But Learning-gem5 or tutorial is not supported this. Through Commmonitor, I can trace the bus between L2Cache and L1DCache, but did not know how to apply the bus invert method. can you tell me which part modified for