Re: [gem5-users] [ARM] Implementing Custom Registers

, Feb 26, 2015 at 7:22 PM, Gutierrez, Anthony via gem5-users gem5-users@gem5.org wrote: What is the exact panic? And where did you insert your asm instructions in the kernel? *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Guru Prasad via gem5-users *Sent:* Thursday

Re: [gem5-users] [ARM] Implementing Custom Registers

wrote: What is the exact panic? And where did you insert your asm instructions in the kernel? *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Guru Prasad via gem5-users *Sent:* Thursday, February 26, 2015 3:52 PM *To:* gem5 users mailing list *Subject:* [gem5-users

Re: [gem5-users] [ARM] Implementing Custom Registers

wrote: What is the exact panic? And where did you insert your asm instructions in the kernel? *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Guru Prasad via gem5-users *Sent:* Thursday, February 26, 2015 3:52 PM *To:* gem5 users mailing list *Subject:* [gem5-users

[gem5-users] [ARM] Implementing Custom Registers

Hi, I'm looking to implement a few custom registers to export some statistics to the kernel. Looking at src/arch/arm/miscregs.hh and src/arch/arm/miscregs.cc, I see how the perf registers are being declared. I followed the same procedure and declared my custom registers above NUM_MISCREGS. I

Re: [gem5-users] Reviewboard registration error

Hi, I am also facing the same issue. I'm posting a screenshot of the same - hoping that it helps in some way. Regards Guru On Thu, Feb 12, 2015 at 5:44 AM, Rizwana Begum via gem5-users gem5-users@gem5.org wrote: Yes. I had tried different user name. Now, I tried on another web browser,

Re: [gem5-users] [arm_detailed] Assertion failure

/Commit_Access says so). Is anyone else having this issue? Thank you, -Rizwana On Tue, Feb 3, 2015 at 4:11 PM, Guru Prasad via gem5-users gem5-users@gem5.org wrote: Hi, I've run into an assertion error while checkpointing with the 'arm_detailed' CPU. I'm using the provided linux

[gem5-users] [arm_detailed] Assertion failure

Hi, I've run into an assertion error while checkpointing with the 'arm_detailed' CPU. I'm using the provided linux-aarch32-ael.img with kernel compiled from master branch of linux-linaro-tracking-gem5. gem5.opt: build/ARM/cpu/o3/fetch_impl.hh:989: bool

Re: [gem5-users] sample program not getting terminated on ARM full system simulation

Ah, I seem to have misunderstood regarding x86 simulations. Okay, first, I'm pretty sure that you cannot run a gcc which was compiled with --target x86* on an ARM machine. I had to cross-compile gdb and put the binary into the image file to use it from within the simulation. This is what you

Re: [gem5-users] sample program not getting terminated on ARM full system simulation

Could you maybe paste the code? I haven't done any x86 simulations, but multiple core runs on ARM simulations have run fine and completed successfully for me. Also, if you're using O3CPU, then long running time is quite possible given that you're stressing the CPU greatly (loop). You could try to

Re: [gem5-users] DVFS does not seem to work on ARM full system simulation

Hi Rahul, I followed the instructions given here http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS, and was able to run and test DVFS. You may also want to read a similar question http://comments.gmane.org/gmane.comp.emulators.m5.users/17881 that I had posed earlier. Hope this helps.

[gem5-users] Debugging Simulated Code - Remote 'g' packet is too long

I followed the instructions given here http://www.m5sim.org/Debugging_Simulated_Code to debug simulated code. I run into the following issue with gdb-7.8.1. (gdb) set remote Z-packet on (gdb) set tdesc filename features/arm-with-neon.xml (gdb) symbol-file linux-linaro-gem5/vmlinux Reading symbols

[gem5-users] DVFS and energy controllers

Hi, I followed the sample code provided in commit 6bbb7ae309 to set up DVFS. This got rid of the warning in Gem5 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. However, the kernel still reports saying [0.366079] gem5_energy_ctrl_mc: gem5_mc_init: No energy controller found Is

Re: [gem5-users] DVFS and energy controllers

Just to follow up, I modified config/example/fs.py to contain the following test_sys.cpu_clk_domain = SrcClockDomain() test_sys.cpu_clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] test_sys.cpu_clk_domain.domain_id = 0 test_sys.cpu_clk_domain.voltage_domain =

Re: [gem5-users] DVFS and energy controllers

Stephan, Thanks. It works perfectly. Apologize for missing it in the documentation. Regards Guru On Fri, Dec 5, 2014 at 11:55 AM, Stephan Diestelhorst via gem5-users gem5-users@gem5.org wrote: Hi Guru, On Friday 05 December 2014 16:42:52 Guru Prasad via gem5-users wrote: I followed

Re: [gem5-users] New ARM Full-System Files

Hi, Are the kernel sources also available? If so, could you please point me to them? On Thu, Oct 30, 2014 at 7:07 PM, Anthony Gutierrez via gem5-users gem5-users@gem5.org wrote: Hello Everyone, There are some new ARM kernels and disk images that work with gem5 for both AArch32 (32-bit)

[gem5-users] Breaking down CPU idle time

Hi, I'm trying to break down CPU idle time into its components. I'm primarily interested in the breakdown of the following: - Time CPU was idle while memory was busy - Time CPU was idle while cache was busy Looking at the code, I think that there is a simple way to identify when the CPU was

Re: [gem5-users] Boot loader issue

Go to gem5_base/system/arm and run make copy the output to gem5_base/system/binaries/ On Sun, Nov 2, 2014 at 9:33 AM, Anmol Mohanty via gem5-users gem5-users@gem5.org wrote: Hi Gem5 community, I am getting this bootloader issue. This has been raised before, I have tried all the steps

[gem5-users] [ARM] Interrupt handling

Hi, I am looking to implement some custom instruction accounting. I tried running some SPEC benchmarks at different frequencies and noticed that the number of instructions vary across runs. I believe this is because of timer based interrupts and thus would like to eliminate these. To do this,

Re: [gem5-users] [ARM] Interrupt handling

way to do this is probably to only count instructions when InUserMode() is true. You could wrap the stat accounting function in this in the o3 commit stage and that would probably solve your problem instead of trying to cache all sources of interrupts. Ali From: Guru Prasad via gem5-users

Re: [gem5-users] [ARM] Interrupt handling

count instructions when InUserMode() is true. You could wrap the stat accounting function in this in the o3 commit stage and that would probably solve your problem instead of trying to cache all sources of interrupts. Ali From: Guru Prasad via gem5-users gem5-users@gem5.org Reply-To: Guru

Re: [gem5-users] Error while running Gem5 simulation from a Java program.

Hi Tod, When you are running a benchmark with the -b option, I believe that the values in configs/common/Benchmarks.py overrides the value provided at the command line. Since you're running this from within Java, I would guess that the M5_PATH environment variable is either not present within the

Re: [gem5-users] Error while running Gem5 simulation from a Java program.

Hi Todd, Apologies on that useless post.. So I tried reproducing the results that you obtained, and sure enough, command line: build/ARM/gem5.opt configs/example/fs.py --kernel=/home/guru/gem5/ kernel/linux-3.3-armdroid/vmlinux --disk-image=/home/guru/gem5/gem5-stable/syste

Re: [gem5-users] Error while running Gem5 simulation from a Java program.

Yes, I'm running in FS mode. command line: build/ARM/gem5.opt configs/example/fs.py ... Regards Guru On Mon, May 5, 2014 at 11:39 AM, Tanmay Gadre via gem5-users gem5-users@gem5.org wrote: i meant fs mode On Mon, May 5, 2014 at 8:15 PM, Tod via gem5-users gem5-users@gem5.orgwrote: