[gem5-users] Re: DRAM access rate too high?

are these random addresses that should access > different rows or is this sequential, in which case, the data will sequence > across the column addresses within the same row. > > Thanks, > Wendy > > On 5/6/21, 11:37 AM, "Joardar, Biresh Kumar via gem5-users" &g

[gem5-users] DRAM access rate too high?

Hello, I’m simulating a 4-core system connected to 1 DRAM bank. For this purpose, I set both the variables ‘ranks_per_channel’ and ‘banks_per_rank’ in the file src/mem/DRAMInterface.py to 1, and then recompile Gem5. Next, I run a single-thread test workload that has 95% cache miss rate and

[gem5-users] Re: understanding commMonitor output

<https://urldefense.com/v3/__https://stackoverflow.com/questions/61052733/obtaining-physical-address-trace-from-gem5__;!!JmPEgBY0HMszNaDT!6KAoPFlm0TG-aF31j_89oRtO8fFJZ6VO92OIJofjRtTTZmxZBAGqU1z6zR-sdwphwBqV$>. Greetings, Miguel Antonio Avargues Gutiérrez. El 31/03/2021 a las 18:57, Joardar, Bire

[gem5-users] understanding commMonitor output

Hello, I intend to observe all the physical DRAM addresses that are accessed when an application is being executed in full-system mode. Following some earlier discussions on this mailing list, I used the commMonitor. I added the following lines to fs.py file: test_sys.monitor = CommMonitor()