Hello Everyone and Gabe, Does x86 gem5 SE mode using O3CPU considers timing delays of TLB Hit and TLB miss? If yes, which file has it?
I could not find any timing parameter in src/arch/tlb.cc in translate timing function Is that timing delay overlapped with the cache access timing delay? Also, how is the tlb function invoked, is it invoked through iew files or lsq files for data tlb?
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
