Hi All, I am trying to simulate a scenario where I want a TimingSimpleCPU connected to a TLM memory and this is causing a segfault in gem5::MemPool::freePageAddr. Can you help me understand/progress from this issue?
I followed the instructions in util/tlm/README as follows: In util/tlm 1. ../../build/ARM/gem5.opt ../../configs/example/se.py --cpu-type=TimingSimpleCPU --tlm-memory=transactor --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 -c ../../tests/test-progs/hello/bin/arm/linux/hello --mem-size=512MB The above step generated the config.ini 2. ./build/examples/slave_port/gem5.sc m5out/config.ini The above step is causing a segfault. I tried to do debug using gdb and below is the call stack *"0 s (=) : sc_main Start of Simulation* *Program received signal SIGSEGV, Segmentation fault.gem5::MemPool::freePageAddr (this=this@entry=0x0) at build/ARM/sim/mem_pool.cc:6969 return freePageNum << pageShift;(gdb) bt#0 gem5::MemPool::freePageAddr (this=this@entry=0x0) at build/ARM/sim/mem_pool.cc:69#1 0x00007ffff71268ac in gem5::MemPool::allocate (this=0x0, npages=1) at build/ARM/sim/mem_pool.cc:117#2 0x00007ffff713b17b in gem5::Process::allocateMem (this=0x6e2560, vaddr=<optimized out>, size=4096, clobber=clobber@entry=false) at build/ARM/sim/process.cc:339#3 0x00007ffff6b06313 in gem5::SETranslatingPortProxy::fixupRange (this=0x760340, range=..., mode=gem5::BaseMMU::Write) at build/ARM/mem/se_translating_port_proxy.cc:62#4 0x00007ffff6b05a53 in gem5::TranslatingPortProxy::tryOnBlob(gem5::BaseMMU::Mode, std::unique_ptr<gem5::TranslationGen, std::default_delete<gem5::TranslationGen> >, std::function<void (gem5::TranslationGen::Range const&)>) const (this=0x760340, mode=gem5::BaseMMU::Write, gen=..., func=...) at build/ARM/mem/translation_gen.hh:219#5 0x00007ffff6b060f8 in gem5::TranslatingPortProxy::tryWriteBlob (this=0x760340, addr=32768, p=<optimized out>, size=<optimized out>) at /home/utils/gcc-9.3.0-binutils-2.33.1/include/c++/9.3.0/new:174#6 0x00007ffff5f95bd8 in gem5::PortProxy::writeBlob (size=<optimized out>, p=<optimized out>, addr=<optimized out>, this=0x760340) at build/ARM/base/loader/memory_image.cc:50#7 gem5::loader::MemoryImage::writeSegment (this=this@entry=0x6e2678, seg=..., proxy=...) at build/ARM/base/loader/memory_image.cc:44#8 0x00007ffff5f95ca7 in gem5::loader::MemoryImage::write (this=this@entry=0x6e2678, proxy=...) at build/ARM/base/loader/memory_image.cc:57#9 0x00007ffff713aea5 in gem5::Process::initState (this=this@entry=0x6e2560) at build/ARM/sim/process.cc:305#10 0x00007ffff5193cf0 in gem5::ArmProcess32::initState (this=this@entry=0x6e2560) at build/ARM/arch/arm/process.cc:109#11 0x00007ffff50a0d09 in gem5::ArmLinuxProcess32::initState (this=0x6e2560) at build/ARM/arch/arm/linux/process.cc:68#12 0x00007ffff70bcdc7 in gem5::CxxConfigManager::forEachObject (this=this@entry=0x621770, mem_func=&virtual table offset 48) at build/ARM/sim/cxx_manager.cc:591#13 0x00007ffff70bd53b in gem5::CxxConfigManager::initState (this=0x621770) at build/ARM/sim/cxx_manager.cc:619#14 0x000000000041dc5c in Gem5SystemC::Gem5SimControl::end_of_elaboration() ()#15 0x000000000043de3e in sc_core::sc_module::elaboration_done(bool&) ()#16 0x0000000000441473 in sc_core::sc_module_registry::elaboration_done() ()#17 0x000000000044c851 in sc_core::sc_simcontext::elaborate() ()#18 0x000000000044f1a1 in sc_core::sc_simcontext::initialize(bool, bool) ()#19 0x000000000044f26e in sc_core::sc_simcontext::initialize(bool) ()#20 0x000000000044f292 in sc_core::sc_simcontext::simulate(sc_core::sc_time const&) ()#21 0x000000000044f53b in sc_core::sc_start(sc_core::sc_time const&, sc_core::sc_starvation_policy) ()#22 0x000000000044f671 in sc_core::sc_start() ()#23 0x000000000040d270 in sc_main ()#24 0x000000000043a19d in sc_elab_and_sim ()#25 0x0000000000439f53 in main ()"* -- Thanks Siva
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