Hi all, I am aware that we can set latencies on an opClass basis (ex. MemRead) for the O3_ARM_v7a CPU, but is it possible to set instruction-specific (ex. LDREX) latencies?
Thanks, Paul
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users