Hi Ayaz,
(1) I want to model VIPT cache in gem5 under Ruby system, but Ruby does not
seem to call the method in the classic system, that is, the script in the
src/mem/cache . Which files should I modify to model VIPT in Ruby?
(2) According to my understanding of VIPT and PIPT, the latency
Hi Leon,
I think you can use lower than normal latency values (what would be
reasonable for PIPT) to model VIPT cache in gem5. To understand how to
configure cache latencies, have a look here (if you have not already):
https://www.gem5.org/documentation/learning_gem5/part1/cache_config/
-Ayaz
Hi Ayaz,
Sorry to bother you again, but the aforementioned approach that you proposed to
model a VIPT in gem5 has struck me lately, since implementing a real VIPT is,
now I see, not worth the fight. Any chance you could elaborate on your earlier
proposition? Like, what latency I can change and
Hi Ayaz,
Thank you so much for your instructions and I will look into it. By the way, if
you have any more information on implementing VIPT in gem5, please let me know!
Thanks again for your help.
___
gem5-users mailing list -- gem5-users@gem5.org
To
Hi,
I am not totally sure how easy would it be to modify the current
implementation, but following pointers to understand the codebase and where
to make modifications might be useful:
to understand how virtual to physical address translation takes place look
at:
src/arch/[your ISA e.g.
Hi Ayaz,
Thank you for your reply. In spite of your proposal, I still hope to implement
real VIPT in gem5 (20.0.0.3). If I'm to do that, do you know what files I
should modify or add and maybe something important to notice?
Looking forward to your reply!
Hi Leon,
Since, gem5's caches are PIPT so there should not be an aliasing problem
and you can change the latency of the cache to model a VIPT cache. Since, a
VIPT cache should not have aliasing problem if all index bits come from the
page offset (as far as I understand), maybe for a realistic
Hi Ayaz,
I can't thank you enough for you reply. I'm aware of the fact that from
software's perspective, VIPT and PIPT should be functioning equally but what
piqued my interest is what it looks like from hardware's perspective.
Let's say both i-cache and d-cache are working under PIPT, do you
Hi Leon,
In gem5, the caches are PIPT technically. But, you can model the timing of
a VIPT cache by changing the latency of your cache. As far as the kernel
boot log is concerned, I am not fully sure if "CPU: PIPT / VIPT nonaliasing
data cache, PIPT instruction cache" refers to the actual
