Hi Aritra,
Your observation on what we model is correct. The response_latency is
the delay between the time that we handle a response from below (e.g.,
main memory) to the time we will send the response above (e.g., response
to the L2). We don't really attribute this latency to any specific
Hi Nikos,
Thanks for your response.
For a packet which is a miss at L3, I have observed that the time its
response packet takes for reaching the cpu_side port of L3 from the
mem_side port of L3 (after the data is fetched from the main memory and
available at the mem_side port of L3) is always
Hi,
The response_latency doesn't necessarily correspond to the time it takes
to fill in with the data from the response, but rather the time it takes
for a cache to respond to a request from the point it has the data. In
some cache designs, this will include the time to fill in but in other
Hi all,
I didn't hear from anybody. So this is just a gentle reminder. It would be
helpful if someone can respond. Thanks!
On Tue, 8 Sep, 2020, 12:00 PM Aritra Bagchi,
wrote:
> Hi all,
> I am using classic cache models in gem5. I have three levels of
> caches in the hierarchy: L1-D/I,
