Hi Deepak, RISC-V PMA is supported in gem5. You can have a look at the source here: https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/riscv/PMAChecker.py
Also, here is an example of how this can be used in the gem5 config script: https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-fs/configs-riscv-fs/system/system.py#214 -Ayaz On Tue, Jun 15, 2021 at 1:23 PM Deepak Mohan via gem5-users < gem5-users@gem5.org> wrote: > Hi, > I was writing an OS that can run on RISC-V FS mode in gem5. I want > to make certain address ranges uncacheable (for some memory mapped > devices). RISCV page table entries doesn't provide any flags to > achieve this. The proper way to do this in RISCV seems to be using PMA > (Physical Memory Attributes), but I couldn't find any implementations > of PMA in gem5. Is PMA implemented for RISCV in gem5 ? Is this the > right approach to solve this problem ? Can anybody give me any ideas > to solve this problem ? It will be great if anyone can provide some > ideas. > > Thanks, > Deepak Mohan > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
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