Hi Samuel, If you're using the classic memory system, the easiest option is to add a tiny cache between the SimObject that issues the writes and the rest of the memory system. Then your SimObject can issue simple WriteReqs and the cache will take care of the rest.
Otherwise, you will have to implement part of the coherence protocol in your SimObject (in your case a write will have to fetch an exclusive copy of the cache line with a ReadExReq, update the cache line and write it back with a WritebackDirty). Hope this helps. Thanks, Nikos On 30/06/2021 13:36, Samuel Thomas via gem5-users wrote:
Hello all, I am running into issues where I am trying to create packets to perform writes in my system that originate outside the CPU. Without knowledge of which MemCmds do what, I naïvely declared them as WriteReqs, but there seem to be response packets that make it back to the CPU which causes the system to crash. Does anyone know of a good place to read about the different MemCmds (either gem5 related or otherwise)? Thank you for your help! Best, Sam _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
