I think you can try with COSSIM That enables to run heterogeneous systems. Best
On Sat, 27 Jun 2020, 3:43 pm Ciro Santilli via gem5-users, < gem5-users@gem5.org> wrote: > I'm not sure about the TLB part, but > configs/example/arm/fs_bigLITTLE.py in tree already showcases two > types of cores and is maintained, so maybe you can take that as a > starting point and see how TLBs are attached and modify that for one > of the set of cores. > > On Fri, Jun 26, 2020 at 11:31 PM Choe, Jiwon via gem5-users > <gem5-users@gem5.org> wrote: > > > > Hi all, > > > > I was wondering if the following would be possible with a gem5 > full-system simulation, and I thought this would be the best place to ask. > > > > I want to simulate a multicore system with two different configurations > of cores coexisting in the same system. One set of the cores (I'll call > this A-type cores) would be configured in a "normal" way with the usual > layers of caches and TLBs, but the other set of cores (B-type cores) would > be configured such that it bypasses all caches, doesn't use TLBs, and is > instead connected straight to memory. > > > > If such a system can be configured, would it also be possible to execute > a program on this simulated system so that > > 1) the program mainly runs only on the A-type cores, > > 2) but a thread can be spawned from the program in a normal way (using > pthread libraries, for example) and mapped to run on a B-type core? > > > > Please let me know if any part of my question needs clarification. > > > > Thanks in advance, > > Jiwon > > _______________________________________________ > > gem5-users mailing list -- gem5-users@gem5.org > > To unsubscribe send an email to gem5-users-le...@gem5.org > > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
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