On 7/11/2023 5:46 PM, Ayaz Akram via gem5-users wrote:
Hi Eliot,
Based on my understanding, when pkt->makeResponse() is called it updates the "cmd" of the pkt with
the appropriate responseCommand (this line of code: cmd = cmd.responseCommand();) . If you look at
"MemCmd::commandInfo[]" in pa
Thank you Elliot and Ayaz for the well explained responses. I understood
the code snippet now.
On Tue, Jul 11, 2023 at 5:46 PM Ayaz Akram wrote:
> Hi Eliot,
>
> Based on my understanding, when pkt->makeResponse() is called it updates
> the "cmd" of the pkt with the appropriate responseCommand (t
Hi Eliot,
Based on my understanding, when pkt->makeResponse() is called it updates
the "cmd" of the pkt with the appropriate responseCommand (this line of
code: cmd = cmd.responseCommand();) . If you look at
"MemCmd::commandInfo[]" in packet.cc, the response command for a
"WriteReq" command is "W
On 7/11/2023 3:03 PM, John Smith wrote:
Thanks for responding, Elliot. I somewhat understand that after the write is accomplished, the
returning packet won't have the data. But still, why is the returned value 0 in that case? Shouldn't
it still be equal to the memory access latency.
In the Ato
On 7/11/2023 3:20 PM, Ayaz Akram via gem5-users wrote:
Hi John,
If you are checking if the pkt is write when pkt->hasData() condition is true in recvAtomicLogic()
function, the check (pkt_is_write) will always be false. The reason is that a write pkt would have
already written its data to the
Hi John,
If you are checking if the pkt is write when pkt->hasData() condition is
true in recvAtomicLogic() function, the check (pkt_is_write) will always be
false. The reason is that a write pkt would have already written its data
to the memory (abstract memory) in the previous line of code
"mem_
Thanks for responding, Elliot. I somewhat understand that after the write
is accomplished, the returning packet won't have the data. But still, why
is the returned value 0 in that case? Shouldn't it still be equal to the
memory access latency.
On Tue, Jul 11, 2023 at 2:34 PM Eliot Moss wrote:
>
On 7/11/2023 1:28 PM, John Smith via gem5-users wrote:
So, I used the function pkt->isWrite() to check if the packet is a write request. And I observed
that inside the pkt->hasData() if condition, pkt->isWrite() returned false. Hence only the read
packets were entering the if(pkt->hasData()) con
So, I used the function pkt->isWrite() to check if the packet is a write
request. And I observed that inside the pkt->hasData() if condition,
pkt->isWrite() returned false. Hence only the read packets were entering
the if(pkt->hasData()) condition
On Tue, Jul 11, 2023 at 1:10 PM Eliot Moss wrote:
On 7/11/2023 1:01 PM, Eliot Moss wrote:
On 7/11/2023 12:52 PM, John Smith wrote:
Okay, but I've also noticed that a WriteReq generally carries no data. Why exactly is that? Cause
if we are writing to memory, then the memory access latency shouldn't be 0 right?
I believe that happens if the wri
On 7/11/2023 12:52 PM, John Smith wrote:
Okay, but I've also noticed that a WriteReq generally carries no data. Why exactly is that? Cause if
we are writing to memory, then the memory access latency shouldn't be 0 right?
I believe that happens if the write got its data by snooping a cache.
The
Okay, but I've also noticed that a WriteReq generally carries no data. Why
exactly is that? Cause if we are writing to memory, then the memory access
latency shouldn't be 0 right?
On Tue, Jul 11, 2023 at 12:49 PM Eliot Moss wrote:
> On 7/11/2023 12:37 PM, John Smith via gem5-users wrote:
> > Hi
On 7/11/2023 12:37 PM, John Smith via gem5-users wrote:
Hi everyone,
Could someone please help me with explaining what's happening in the below code snippet? It's the
receiveAtomicLogic() function in mem_ctrl.cc. Why are we returning the latency as 0 if the packet
doesn't have any data? And in
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