Hi everyone, Is it possible to send more than one memory request from the dcacheport to the memory system without stalling the pipeline. What i have seen so far is that when one memory instruction is send to the memory, then another memory request cannot be send to the memory as sendTimingReq returns boolean type false. And it has to wait until the previous memory response is back then issue the next one .
My goal is to allow the MinorCPU to have overlapping memory requests to the memory, therefore is it possible to achieve this by sending more than one memory request to the memory? as I cannot figure this out. I am currently using noncoherent Xbars to connect my caches and the memory system, would I need to change it or is there something else that i have to do? Any help would be appreciated. Thanks.
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