I am running Gem5, X86, SE mode in 4 cores with CPU running at 3GHz (set using --cpu-clock in Options.py), L1, L2 are private and L3 is shared. I am using classic cache.
``` system.l3.demand_avg_miss_latency::.cpu0.data 3861061.012024 # average overall miss latency ``` I am a little confused about the ***average miss latency values*** reported by Gem5 stats, since the value is ***3861061 cycles*** which ~ 1.2 ms (considering 3GHz CPU clock). Isn't too high latency to access memory on an average considering memory access times are always mentioned as 100s of CPU cycles. I am using [NVMainMemory][1] as main memory,but still avg access time in milliseconds does not fit in. Am I missing something here? Thanks Arun [1]: https://github.com/SEAL-UCSB/NVmain
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