[gem5-users] MOESI protocol study

Dear All, I want to study the MOESI cache coherence protocol. Can anyone suggest some study material that can be useful in understanding MOESI protocol for cache coherence. Many Thanks Avais ___ gem5-users mailing list

Re: [gem5-users] MOESI protocol study

Avais,I think the standard textbook is:Sorin, Hill, Wood: A Primer on Memory Consistency and Cache Coherence.  Published by Morgan and Claypool.Boris-"gem5-users" wrote: -To: gem5 users mailing list From: Muhammad Avais

[gem5-users] Observing ReadReq in writeQueue

Hey guys, Could you please help me understand why writeQueue is having ReadReq packets in it. Debug statements - ===WRITE QUEUE=== 2559455250: system.mem_ctrls: Write 10632576, command: ReadExReq, ContextId: 1, MasterId: 18 2559455250: system.mem_ctrls: Write 1766829376, command: ReadReq,

Re: [gem5-users] MOESI protocol study

Dear Boris, Thanks for help. Best Regards Avais On Fri, Oct 20, 2017 at 3:46 AM, Boris Shingarov wrote: > Avais, > > I think the standard textbook is: > Sorin, Hill, Wood: A Primer on Memory Consistency and Cache Coherence. > Published by Morgan and

Re: [gem5-users] ARM v8 KVM - GEM5

Hi All, Any idea why the ARM KVM model is not running in the following, please ? If I need to debug this, can someone suggest what debug flags should I be looking out for ? Thank you Regards Yasir From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Qureshi Yasir Mahmood Sent:

Re: [gem5-users] [EXT] Re: ARM v8 KVM - GEM5

I'm afraid I can't help you with this directly, but one idea might be to run your commands through 'strace' and see how gem5 is trying to access /dev/kvm and how the kernel is reacting to these accesses. From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Qureshi Yasir Mahmood