Re: [gem5-users] Terminating multi-core simulation

2018-05-29 Thread Muhammad Avais
Dear Haeyoon, Many thanks for your help and guidance. I will try to apply first scheme suggested by you in previous email. Best Regards, Avais On Mon, May 28, 2018 at 1:18 PM, 조해윤 wrote: > Dear Avais, > > I think it is reasonable to normalize with the numbers of executed >

[gem5-users] Memory models possibilities

2018-05-29 Thread Richard Brown
Hello everyone, I have been reading several posts in this forum and the gem5 documentation, I am new with gem5, I have to work with memory subsystem and I have already changed characteristics on main memory and cache memory as train. However I have some questions that I have not answered reading

[gem5-users] x86 instructions with microops

2018-05-29 Thread Tariq Azmy
Hi, How is a particular instruction being decoded, especially when it has micro-ops? I looked at the stats in commit_impl.hh if (!inst->isMicroop() || inst->isLastMicroop()) instsCommitted[tid]++; opsCommitted[tid]++; Does this means the micro ops is also stored as a Dynamic Inst, with

Re: [gem5-users] Issues in handling compressed data for L3 cache

2018-05-29 Thread Jason Lowe-Power
Hi Srajan, Could you post this on our code review site so the patch creator (Daniel) can take a look? You can register on the site with a google account (e.g., your gmail). Then, you can post a reply on this page: https://gem5-review.googlesource.com/c/public/gem5/+/9741. One possible source of

Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

2018-05-29 Thread 조해윤
Dear Mitali Sinha. In my case, I run moby bench with RealView_PBX machine type. I don't know if it is the cause, but give it a try. Best Regard, Haeyoon Cho. 2018-05-29 20:39 GMT+09:00 Mitali Sinha : > I have followed the instructions provided in the gem5.org website to run > the Moby

[gem5-users] Error in running Moby(Asimbench) benchmark in gem5

2018-05-29 Thread Mitali Sinha
I have followed the instructions provided in the gem5.org website to run the Moby benchmarks on gem5 as follows: 1. Downloaded the Asimbench from https://bitbucket.org/yongbing_huang/asimbench/downloads/ which contains the following folders and files: 1. asimbench_android_arm_kernel :

Re: [gem5-users] Issues in handling compressed data for L3 cache

2018-05-29 Thread Srajan Khare
Hi Jason, As per your suggestion I included the recently committed patch (for creating sector cache) with my gem5 version. Then after, just to get an idea of Sector Cache performance, I ran simulation for *bzip2 *SPEC CPU2006 benchmark with 1B fast forward and then executing 500M instruction in

Re: [gem5-users] Issues in handling compressed data for L3 cache

2018-05-29 Thread Srajan Khare
Thank you Jason for your quick reply! On Sat, May 19, 2018 at 12:50 PM, Srajan Khare wrote: > Hi friends, > > I have been implementing Cache Compression algorithm in gem5. > So in order to tap data for all the writes into L3 cache I have been using > handleFill() function in cache.cc file. I