[gem5-users] The questions about TTBR0 update cycles

Hi guys, I evaluated the TTBR0 update costs in Gem5 ARM (FS mode), the result was about 6 cycles. The simulated environment is the Minor CPU (specifically, HPI mode). The test code is just like the following: begin_ticks= read_ticks(); __asm__

Re: [gem5-users] The questions about TTBR0 update cycles

Hi Dong, At the moment gem5 does not model the timing for flushing the TLB, that is the cost of going through the TLB entries and invalidating them. However, you will see that subsequent code will trigger TLB misses and and will run slower (compared to what you would get if you run the same code

[gem5-users] network test with iperf and/or netperf

Hi all I want to have a network test on full system image of ARM and X86 on gem5. is it possible to test using Iperf and/or Netperf? if so how? attach me a link. pls If not, is there any possible test mechanism to be applied for testing installed full system gem5? regards Biruk -- *Biruk