[gem5-users] PCI operation ordering

Hi, We have been using gem5 with the classic memory system for a while for full system X86 simulations integrating a number of different more modern PCIe device models. Now we are trying to get things to work with Ruby as well for multi-core X86 simulations. Currently we are tracking down some

[gem5-users] Cannot enter benchmark test set.

I defined TLB object tlb2 in mmu.cc file, and added tlb2 access process in getTE() function of tlb.cc file to realize simple two-level TLB. It can be compiled successfully, but it can't enter benchmark test set at runtime. I used Command line is：./build/ARM/gem5.opt

[gem5-users] SPEC2017 in FS mode

Hi, I've tried running the SPEC2017 benchmarks in FS mode of gem5 using the instructions/files provided by the gem5 resources page. https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017 I've also followed the step by step instructions in the git repo for