Hello everyone,
I am trying to write data to a memory mapped queue in gem5. I have created a
queue as a SimObject which is connected by PIO port. I am working on SE mode
and want to enqueue data to the queue from the user-mode program.
The device registers has been mapped to the program
Hi Gabe,
I think your code has not yet made into stable/master branch. I see that in
develop branch INTREG_IMPLICIT is no longer there and is replaced by
INTREG_PRODHI and INTREG_PRODLO
However, I see that even in develop branch there are two classes that are
generated - Mul1s and
Hey,
Thanks! Yes, the configuration is the same. Now, with the compiled
bootloader it boots up with 4 cores.
On Thu, Jul 22, 2021 at 10:05 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:
> Hi Majid,
>
> Out of curiosity, are you sure the configuration is the same? Could you
> try to
Yes, I haven't looked at the code itself, but that explanation seems very
plausible. The way the ISA parser works is basically if something is on the
left hand side of an =, then it's assumed to be a destination, and
otherwise it's a source. It bases its decision *purely* on text, with no