hello！
i am using gem5's KVM to accelerate my simulation, but in version 22.0, I
encountered the following issue:
REAL SIMULATION
build/ARM/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config.
build/ARM/dev/arm/energy_ctrl.cc:252: warn: Existing EnergyCtrl, but no
In my code I'll have a simobject which has its own cache. As classical
cache use CpuSidePort and MemSidePort to receive and respond to request, I
want to create some internal CpuSidePort and MemSidePort in my simobject
like below
> class SimObject : public ClockedObject
> {
> Cache cache;
>
On 8/14/2023 11:58 AM, Khan Shaikhul Hadi via gem5-users wrote:
In my code I'll have a simobject which has its own cache. As classical cache use CpuSidePort and
MemSidePort to receive and respond to request, I want to create some internal CpuSidePort and
MemSidePort in my simobject like below
Hi everyone,
I ran the following program which simply reads the value of MiscReg
(mhartid, mstatus, ...),
https://pastebin.com/t5XBBWEz. (remove line 31-32)
The compilation command I used is, riscv64-unknown-elf-gcc -static hello1.c
-o hello1.
I ran it with SE script, gem5.opt se.py -c hello1
Hey,
SE mode runs things in user space, you cannot run privileged instructions in
it.
If you wish to support privilege levels then you'll need to build an FS mode
simulation.
Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616
web:
On 8/14/2023 3:47 PM, Khan Shaikhul Hadi wrote:
Instead of directly connecting all level 1 caches ( icache, dcache etc) to CPU and next level bus, I
want to create a controller module that will have all those caches . This controller module will
receive all cpu requests and distribute them to
On 8/14/2023 1:42 PM, Khan Shaikhul Hadi wrote:
Initially I was thinking doing something like this as you suggested:
CpuSidePort cacheMemSidePortConnection = cache.memSidePort;
MemSidePort cacheCpuSidePortConnection = cache.cpuSidePort;
problem is when I looked into how python code
