Re: [gem5-users] Safety of SnoopMask Extension

[Andreas Hansson]

Hi Vanchinathan,

It should be safe, but will probably have performance implications (and it’s 
technically not part of the standard).

I would think you’re likely to want L2’s per core, or up to possibly 4 core or 
so, and then a crossbar for interleaving across L3s. If you build these more 
sensible topologies you should not have problems.

The system you describe is rather unrealistic…

Andreas

From: gem5-users 
> on behalf of 
Vanchinathan Venkataramani >
Reply-To: gem5 users mailing list 
>
Date: Wednesday, 27 July 2016 at 06:09
To: gem5 users mailing list >
Subject: [gem5-users] Safety of SnoopMask Extension

Hello all

I am trying to run 64 cores, ARMV8, FS with Classic Memory on gem5.

I found that the current SnoopMask can only support 64 connections and hence 
cannot be used to model more than 32 cores or more with separate L1 I- and 
D-Cache. This forced me to change the data type from uint64_t to uint128_t and 
modify some ostream related functions.

This change works fine for the tested benchmark, However, I would like to know 
if this safe.

Thanks a lot in advance!.
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[gem5-users] Micro-op Data Dependency

[Alec Roelke]

Hello,

I'm trying to add an ISA to gem5 which has several atomic read-modify-write
instructions.  Currently I have them implemented as pairs of micro-ops
which read data in the first operation and then modify-write in the
second.  This works for the simple CPU model, but runs into trouble for the
minor and O3 models, which want to execute the modify-write half before the
load half is complete.  I tried forcing both parts of the instruction to
have the same src and dest register indices, but that causes other problems
with the O3 model.

Is there a way to indicate that there is a data dependency between the two
micro-ops in the instruction?  Or, better yet, is there a way I could
somehow have two memory accesses in one instruction without having to split
it into micro-ops?

Thanks,
Alec Roelke
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[gem5-users] Safety of SnoopMask Extension

[Vanchinathan Venkataramani]

Hello all

I am trying to run 64 cores, ARMV8, FS with Classic Memory on gem5.

I found that the current SnoopMask can only support 64 connections and
hence cannot be used to model more than 32 cores or more with separate L1
I- and D-Cache. This forced me to change the data type from uint64_t to
uint128_t and modify some ostream related functions.

This change works fine for the tested benchmark, However, I would like to
know if this safe.

Thanks a lot in advance!.
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