[gem5-users] How to run an application on Gem5

[Umair Khan]

Hi,

I am working on gem5 and I want to run RSA algorithms on gem5 and monitor
its memory access pattern but i dont know how to do it. I searched gem5
website alot and also online stuff related to gem5 but could not got any
useful information. I have also set up full system mode for ARM, Alpha ,
and x86. when i run the full system mode i connect the telnet 3456 as
suggested in gem5 tutorial but then i dont know what are the commands to
execute or what is the purpose of connecting with other shell. Plz help me
as i am stuck in this problem for almost more than 2 weeks. Your help will
be appreciated. Thanks
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Re: [gem5-users] dist-gem5

[Biruk Yirga]

Hi All,
I did run the dist-gem5 for four systems, mean 1 server and the other 3
clients.
My intention is to create communication between them,
now i could see their out put from rundir directory but does not let me to
login and test ping among them if they communicate or not.
- would you share me an idea *how to log into the simulated systems? *
I tried "ssh,m5term,and telnet" + localhost + port number even the host IP
+port number, resulting unknown address
  Thank you for your time in advance.. Biruk

On Mon, Jul 10, 2017 at 7:00 PM, Biruk Yirga  wrote:

> Hi Mohammad and Hi all
> these days I am trying to run dist-gem 5 for my further study,
> but still I am not successful, and I tried many possible approaches, using
>  https://publish.illinois.edu/icsl-pdgem5/getting-started-with-dist-gem5/
>  an other resources frm the web.
>  is there a need to add my own script, to run dist gem5?
> I was totally depend on resources from gem5.
> I have attached the screenshot of my problem,
> Would some one tell me the procedure how to run dist-gem5?
> regards
> *Biruk*
>
>
> --
>
> *Biruk Yirga Nidaw **브루크 이르가 느다우*
>
>  < bir...@etri.re.kr >, birukj...@gmail.com
>
> *ET**R**I*  *한국전자통신연구원*
>
> Electronics and Telecommunications Research Institute
>
> Basic Research Center for Software, Building 07-floor 5 office No. 548
>
> 218, Gajeong-ro, Yuseong-gu, Daejeon, 305-700, KOREA *Tel: 010-3133-3008*
>



-- 

*Biruk Yirga Nidaw **브루크 이르가 느다우*

 < bir...@etri.re.kr >, birukj...@gmail.com

*ET**R**I*  *한국전자통신연구원*

Electronics and Telecommunications Research Institute

Basic Research Center for Software, Building 07-floor 5 office No. 548

218, Gajeong-ro, Yuseong-gu, Daejeon, 305-700, KOREA *Tel: 010-3133-3008*
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Re: [gem5-users] add parameter in params

[raziye deylamsalehi]

Hi Jason

yes I add the parameter in GarnetNetworkInterface in GarnetNetwork.py and
the parameter be assigned to it. my problem is that I want to pass value to
GarnetNetworkInterface when NI's object created in GarnetNetwork. how can pass
this value to f.e. m_num_vcs?
I brought this call in my previous  email.

Thank you.

On Sat, Jul 15, 2017 at 1:06 AM, raziye deylamsalehi <
raziye.deylamsal...@gmail.com> wrote:

> Hi  Jason
>
> Thank you. I look at http://learning.gem5.org/book. but in newer version
> of gem5 used ClockedObjectParams (that inherits from SimObjectParamsa) to
> define constructor's parameter list.
>
> my problem is that I want to initialize those const params when new
> object of class was created. for example:
> in older version of gem5, in src/mem/ruby/network/garnet/
> flexible-pipeline/GarnetNetwork.cc was called networkinterface like this:
>
> for (int i=0; i < m_nodes; i++) {
>NetworkInterface *ni = new NetworkInterface(i, m_virtual_networks,
>
> this);
>ni->addNode(m_toNetQueues[i], m_fromNetQueues[i]);
>m_ni_ptr_vector.push_back(ni);
>  }
>
> but in newer version it was modified to:
>
> for (int i=0; i < m_nodes; i++) {
>
>NetworkInterface *ni = safe_cast(p->netifs[i]);
>m_nis.push_back(ni);
> }
>
> now I want to add my new parameter to constructor of NetworkInterface (I added
> this parameter) and initialize like older version in GarnetNetwork.cc .
> how can I do it>
>
> Thank you.
>
>
> On Wed, Jul 12, 2017 at 6:05 PM, Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> Have a look at http://learning.gem5.org/book to get an overview of how
>> SimObjects and parameters work in gem5.
>>
>> Jason
>>
>> On Tue, Jul 11, 2017 at 2:38 PM Mahmood Naderan 
>> wrote:
>>
>>> The idea is to add some params in .py file and then bind their names to
>>> the variables in the implementation file of of the class (foo.cc). I think
>>> you missed that step. Have a look at the constructor and add yours similar
>>> to the existing params.
>>>
>>>
>>> At least this is the way that we did. I don't know if that procedure has
>>> been changed in newer versions.
>>>
>>> Regards,
>>> Mahmood
>>>
>>>
>>>
>>> On Tue, Jul 11, 2017 at 11:01 PM, raziye deylamsalehi <
>>> raziye.deylamsal...@gmail.com> wrote:
>>>
 Hi Mahmood

 Thank you for answering. for example I want to add parameter to
 src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh. G
 arnetNetworkInterface class is in GarnetNetwork.py file. I added new p
 arameter in .py file and recompile but it said:
  error: 'const Params' has no member named 'num_vcs'
 I didn't add this parameter to  build/x86/params/GarnetNetworkInterface.hh
 for previous run.
 then I added parameter to  build/x86/params/GarnetNetworkInterface.hh and
 recompiled again and it had no compile error.
 then I give input in configs/ruby/Ruby.py but when I simulate my 8*8
 network it has this error:

 system.ruby.network.netifs000.num_vcs without default or user set value

 On Tue, Jul 11, 2017 at 7:37 PM, Mahmood Naderan 
 wrote:

> Hi,
> You have to edit the .py file in the src/ and then recompile. For
> example, have a look at src/mem/cache/BaseCache.py and add your *cache*
> related params there and the recompile. The same can be applied to other
> components.
>
> Regards,
> Mahmood
>
>
>
> On Tue, Jul 11, 2017 at 7:31 PM, raziye deylamsalehi <
> raziye.deylamsal...@gmail.com> wrote:
>
>> Hi
>>
>> I want to add parameter in const params of class. I go to this
>> path build/x86/params and insert parameter there. that is correct?
>>
>> Thanks
>>
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Re: [gem5-users] Non exclusive cache in gem5

[Jason Lowe-Power]

Hi Avais,

I would suggest adding a new "clusivity" which is "non-inclusive" or
whatever you want to call your new inclusion property. Then, you can modify
the maintainClusivity function to act as you want it to.

Jason

On Sat, Jul 15, 2017 at 3:18 AM Muhammad Avais 
wrote:

> Hi
>  Thanks for your response,
>  In 'gem5', i have declared cache 'mostly
> exclusive'  as recommended by you. I have also set "writeback_clean"
> parameter to true of cache which is closer to CPU.
>  Now, i want that this 'mostly exclusive cache,
> should act as 'Non exclusive' cache.
>  Non exclusive cache is cache which does not fill
> on a miss from cache closer to CPU. Also, when some block is accessed from
> Non exclusive cache, it does not invalidate the block.
>  I think in gem5, accessed block from Non
> exclusive cache is invalidated in 'maintainClusivity()' function.
>  I think that by removing the 'maintainClusivity()'
> function, i can make the 'mostly exclusive' cache as 'non exclusive' cache.
>  Is my thinking correct?
>  Also, maintainClusivity() function is used at two
> places in cache.cc file. In 'access()' function and 'recvTimingResp()'
> function.
> I do not understand both functions completely. Can
> anyone suggest, do i need to remove 'maintainClusivity()' function from
> both places or not?
>
> Many Thanks
> Avais
>
>
> On Fri, Jul 14, 2017 at 11:37 PM, Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> The classic cache in gem5 (src/mem/cache and Cache()) is always
>> non-inclusive (i.e., it is neither inclusive nor exclusive). You can set
>> whether it is "mostly-inclusive" or "mostly-exclusive" as a parameter to
>> the Cache SimObject. If the cache is "mostly-exclusive" it will not fill on
>> a miss from a cache closer to the CPU (and the opposite for a
>> mostly-inclusive). Thus, if you want a mostly-exclusive cache, the caches
>> closer to the CPU should set the "writeback_clean" parameter to true (and
>> to false if the further cache is mostly-inclusive).
>>
>> Jason
>>
>> On Fri, Jul 14, 2017 at 3:16 AM Muhammad Avais 
>> wrote:
>>
>>> Dear all,
>>>
>>>  Gem5 supports 'Mostly exclusive' cache. How can i
>>> modify code to make it non exclusive cache.
>>>
>>> I think i can do it by removing maintainClusivity() function from
>>> cache.cc file
>>>
>>> Can someone comment, how to do it
>>>
>>>
>>>
>>> Many Thanks
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[gem5-users] gem5 has encountered a segmentation fault!

[Neu, Markus]

Hallo,


on the try of sending a copy of the data packet to a new module the simulator 
is encountering a segmentation fault. I had extended the cache.cc with a 
additional port and the Cache::recvTimingReq(PacketPtr pkt) with the send 
statement: dapuSidePort->sendAtomic(pkt); for these port. On the other side is 
a simple module which should only receive at the moment from L1i and L1d. The 
template for this is from:

learning.gem5.org/book/_downloads/simple_memobj.cc , i had removed the mem_port 
an extended it with a second master-port.

On execution the first packet is received and than the seg. fault happens.


  0: system.dapu.L1i_port: rcv packet Atomic
  0: system.dapu: rcv packet Atomic
  0: system.dapu:  request pkt recieved: 0xa60 | pc: 0x400a60
  1: system.l2: cache recvTimingReq
gem5 has encountered a segmentation fault!


Unfortunately i am not so experienced with c++ objects. My assumption is the 
objects are wrong defined.


Regards,

Markus Neu
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Re: [gem5-users] Need Linux Kernel with 256 core for X86

[F. A. Faisal]

I tried to use only 4 core with the 2.6.28.4.smp kernel and even then I am
getting the below errors from gem5.
I think the current gem5 version is not capable to run the linux kernel
2.6.28.4.smp (from kernel.org or parsec.m5).
Hence, please let me know what needful to be done to run the 2.6.28.4.smp
kernel in gem5.

./build/X86/gem5.opt configs/example/fs.py --cpu-type=TimingSimpleCPU
--script=script/blackscholes_4c_simsmall.rcS --num-cpus=4 --ruby
--mesh-rows=2 --network=garnet2.0 --topology=Mesh_XY --caches --l2cache
--l2_size=512kB --num-dirs=4 --num-l2=4 --l1d_size=32kB --l1i_size=32kB
--l1d_assoc=2 --l1i_assoc=2
--kernel=/home1/x/3RDCOPY/gem5/X86/binaries/x86_64-vmlinux-2.6.28.4.smp
--disk-image=/home1/x/3RDCOPY/gem5/X86/disks/x86root.img

kernel BUG at arch/x86/kernel/xsave.c:323!


warn: x86 cpuid family 0x: unimplemented function 13


Kernel panic - not syncing: Attempted to kill the idle task!

[ cut here ]

WARNING: at kernel/smp.c:333 smp_call_function_mask+0x1de/0x250()

Modules linked in:

Pid: 0, comm: swapper Tainted: G  D W  2.6.28-rc4-dirty #5

Call Trace:

 [] warn_on_slowpath+0x62/0xa0

 [] vsnprintf+0x449/0x6b0

 [] string+0x34/0xf0

 [] vsnprintf+0x408/0x6b0

 [] up+0xd/0x40

 [] release_console_sem+0x1ae/0x200

 [] stop_this_cpu+0x0/0x30

 [] smp_call_function_mask+0x1de/0x250

 [] vsnprintf+0x268/0x6b0

 [] printk+0x40/0x45

 [] native_smp_send_stop+0x20/0x30

 [] panic+0x82/0x129

 [] do_exit+0x7de/0x890

 [] printk+0x40/0x45

 [] oops_end+0x7a/0xc0

 [] do_invalid_op+0x84/0xa0

 [] xsave_cntxt_init+0x35/0x130

 [] release_console_sem+0x1ae/0x200

 [] up+0xd/0x40

 [] error_exit+0x0/0x51

 [] xsave_cntxt_init+0x35/0x130

 [] xsave_cntxt_init+0x35/0x130

 [] fpu_init+0x4a/0x97

 [] cpu_init+0x319/0x33f

 [] start_kernel+0x1b2/0x321

 [] x86_64_start_kernel+0xd9/0xdd

---[ end trace 4eaa2a86a8e2da22 ]---

Thanks and best regards,

Faisal

On Sat, Jul 15, 2017 at 5:32 AM, Gabe Black  wrote:

> The x86 interrupt controller architecture gem5 implements is described in
> the Intel MultiProcessor Specification which is about 20 years old, and is
> a standard called APIC. Looking at the spec, it has an 8 bit ID register
> and so up to 255 APICs can have unique IDs. I see on the internet folks
> saying the local APICs (ie. the ones attached to each CPU) only have a 4
> bit ID field, so that actually limits you to 15 devices.
>
> If you want to support more CPUs, you'd probably want to implement a new
> standard like xAPIC or x2APIC. xAPIC apparently makes the ID field 8 bits
> again which would make it possible to address 255 CPUs. The little bit of
> the x2APIC spec I looked at seems to say it supports 32 bit IDs, so enough
> that the limit could be considered arbitrarily high, and a logical
> destination addressing scheme (ie. a bit vector of target IDs, I believe)
> which supports a clustering concept which makes it able to address more
> CPUs too.
>
> Gabe
>
> On Fri, Jul 14, 2017 at 8:17 AM,  wrote:
>
>> Thanks for earliest reply.
>>
>> 1. I know how to set the 256 core in Linux kernel using make menuconfig.
>> However, the main problem is the current gem5 version is not even
>> allowing to run the 16 core for Linux kernel 2.6.28.4, which is always
>> showing kernel panic as I mentioned below. Old version like- 2.7.22.9.smp
>> is running fine but I don't have the original package (don't find it in
>> kernel.org). So I can't reset the number of core.
>> 2. My target is to get exactly 256 core benchmark performance. So, I also
>> like to change those files to obtain those results.
>>
>> Thanks and best regards,
>>
>> Faisal
>>
>> On Jul 14, 2017, at 11:32 PM, Jason Lowe-Power 
>> wrote:
>>
>> Hello,
>>
>> A couple of points:
>> 1. You probably will need to compile a custom Linux kernel to support 256
>> cores. This isn't something that is expected to work out of the box.
>> 2. I don't think gem5 supports more than 256 cores (and maybe not that
>> many) without making code modifications. I believe there are a few places
>> where we use a core bitvector, and I doubt it's bigger than 64-bits.
>>
>> Jason
>>
>> On Fri, Jul 14, 2017 at 6:03 AM F. A. Faisal  wrote:
>>
>>> Dear All,
>>>
>>> I basically want to run the benchmarks like- splash or parsec with 256
>>> cores.
>>>
>>> Hence, I tried with X86 ISA with the linux kernel from the Parsec site (
>>> http://www.cs.utexas.edu/~parsec_m5/), which returns the kernel panic
>>> with "warn: x86 cpuid family 0x: unimplemented function 13".
>>>
>>> And even I downloaded the kernel from (https://www.kernel.org/pub/li
>>> nux/kernel/v2.6/) (both .bz2 and .gz), which also returns the kernel
>>> panic with the same warning message (kernel BUG at
>>> arch/x86/kernel/xsave.c:323).
>>>
>>> On the other hand, I download the X86 disk image from-
>>>
>>>  - X86 full system image:
>>> 

[gem5-users] Gem5 running too slow, how to speed up

[赵智慧]

Hello，

 I run an image processing program on gem5 with the SE mode. Using the command: 
./build/X86/gem5.opt configs/example/se.py -c /home/zzh/code/test -o 7 -n 2 
--mem-size=2048MB --caches --l2cache --l2_size 256kB --cpu-clock 1.46GHz 
--cpu-typ=DerivO3CPU




 But it has been running for 6 days，not yet ended，and is still running. 

 How can I accelerate this operation? It costs too much time.


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Re: [gem5-users] undefined reference to `vtable for Port

[Neu, Markus]

Thank you.


Actually i had some incomplete declarations/definitions of virtual methods.


Regards,

Markus Neu


Von: gem5-users  im Auftrag von Oscar Rosell 

Gesendet: Samstag, 15. Juli 2017 18:39
An: gem5 users mailing list
Cc: m5-us...@m5sim.org
Betreff: Re: [gem5-users] undefined reference to `vtable for Port

Hi,

This looks just like a C++ error. Check solution for: 
https://stackoverflow.com/questions/3065154/undefined-reference-to-vtable

Regards,

   Oscar

On 15 Jul 2017, at 17:47, Neu, Markus 
> wrote:

Hallo,

at the moment i try to add a additional port to the 
cache.cc/.hh. The idea is to send a copy of the packets to 
a new module.
I use a example from: 
learning.gem5.org/book/part2/memoryobject.html
 as template for the port implementation. Now i have reached a point were the 
syntax generates no more problems. But the compiler stops with errors:


build/X86/mem/cache/lib.o.partial: In function 
`Cache::DapuSidePort::DapuSidePort(std::__cxx11::basic_string const&, Cache*)':
/home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:204: undefined reference to 
`vtable for Cache::DapuSidePort'
build/X86/mem/cache/lib.o.partial: In function 
`Cache::DapuSidePort::~DapuSidePort()':
/home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:190: undefined reference to 
`vtable for Cache::DapuSidePort'
/home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:190: undefined reference to 
`vtable for Cache::DapuSidePort'
build/X86/exposed_obj/lib.o.partial: In function 
`Dapu::CPUSidePort::CPUSidePort(std::__cxx11::basic_string const&, Dapu*)':
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:43: undefined reference to 
`vtable for Dapu::CPUSidePort'
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:43: undefined reference to 
`vtable for Dapu::CPUSidePort'
build/X86/exposed_obj/lib.o.partial: In function 
`Dapu::CPUSidePort::~CPUSidePort()':
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference to 
`vtable for Dapu::CPUSidePort'
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference to 
`vtable for Dapu::CPUSidePort'
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference to 
`vtable for Dapu::CPUSidePort'
build/X86/exposed_obj/lib.o.partial:/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25:
 more undefined references to `vtable for Dapu::CPUSidePort' follow
collect2: error: ld returned 1 exit status
scons: *** [build/X86/gem5.opt] Error 1


The gem5 version which i use is from today but the template seems to be much 
older. The error massages point to the constructor and class definitions:


Dapu.hh:25 --> class CPUSidePort : public SlavePort

Dapu.hh:43 -->CPUSidePort(const std::string& name, Dapu *owner) :
SlavePort(name, owner), owner(owner), 
needRetry(false),
blockedPacket(nullptr)
{ }


Unfortunately i don't understand what the compiler indicates but would assume a 
missing library. I would appreciate some hints.

Regards,
Markus Neu
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