Re: [gem5-users] (no subject)

[SHARJEEL KHILJI]

Hello
yes if you are using ruby memory system you can select the type of protocol
(e.g., MESI Two level, MOESI CMP Directory etc).

regards,
Muhammad

On 11 October 2017 at 10:51, Muhammad Avais  wrote:

> Hi,
> Does GEM5 follows any specific cache coherence protocol?
>  If yes? then which one?
> Thanks
>
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Re: [gem5-users] Fwd: Issue related to requests having no contextID

[Farshchi, Farzad]

Hi Prakhar,


Use masterId() instead. It return the master name which is set in the Python 
code. Take a look at this code: 
https://github.com/farzadfch/gem5-cache-partitioning/blob/master/cache-part.patch#L158


Farzad


From: gem5-users  on behalf of Prakhar Javre 

Sent: Wednesday, September 20, 2017 4:14 AM
To: gem5-users@gem5.org
Subject: [gem5-users] Fwd: Issue related to requests having no contextID

Hi guys,

We are implementing a scheme for protection against timing channel attacks in 
DRAM controllers. In that, it is required to choose request (for DRAM 
controller) from a specific core at any particular time. While checking for it, 
we found that a lot of requests are not having contextIDs. We also modified 
cache code to assign contextIDs to writeback requests, but apparently, even 
some of the read requests (and other requests also) are not having any 
contextID.  Can you guys help us in figuring out from which place exactly are 
these requests coming?

System config -
2 Cores, L1I, L1D, L2(shared), Prefetch off.

Thanks,
Prakhar Jawre
IIT Kanpur, India

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Re: [gem5-users] Small entry table creation in gem5

[조해윤]

Hello.

I think it depends on the purpose of the table and modeling features.

For example,  let's look a cache tag modeling case.
BaseTags class (/mem/cache/tags/base.hh), which is a kind of table to store
tags, inherits the ClockedObject, because BaseTags needs to model the clock
latency.
However, Cacheset class (/mem/cache/tags/cacheset.hh), which is used in
BaseSetAssoc (it inherits BaseTags class), doesn't inherit any class.
Because, Cacheset is just a data structure, which doesn't model clock
latency.
The latency to access Cacheset (it sounds wired actually, because latency
is for tag access and Cacheset is subset of tag model) is modeled in
BaseSetAssoc class, which inherits ClockedObject.

Haeyoon Cho

2017-10-10 13:17 GMT+09:00 Muhammad Avais :

> Hi,
>
> I want to create small table (256 entries) in gem5 that is accessed on
> each cache miss and follows LRU replacement policy.
>
> Can someone guide me how to do it? (Which classes i should use or inherit)
>
> Many Thanks
>
> Avais
>
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