Re: [gem5-users] Adding a new resource

2018-03-17 Thread Tariq Azmy
By "resources", I assume you are referring to each of the stage in the
out-of-order pipeline? Those stages' implementation codes (fetch, decode,
rename, etc..) are located inside the cpu/o3 directory. Branch prediction
typically is done in fetch stage, so if you look inside the fetch.hh source
code, it includes the header file of "cpu/pred/bpred_unit.hh". So if go up
one level, to the cpu/pred directory, that is where the branch predictor
implementation code is located.

As far as value predictor, I am not sure how you are going to implement it,
but it probably needs to work with or link to other stages/resources such
as iew, instruction queue, rob..

Hope this helps.

On Sat, Mar 17, 2018 at 3:44 PM, Pawan Joshi 
wrote:

> Okay, that makes sense. But isn't there a separate "resources" directory
> where I can see stuff like branch predictors implemented? I don't have any
> br. pred. in my current cpu/o3 directory.
> I wanted that as I can get a template to work with.
>
>
> Pawan
>
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Re: [gem5-users] Adding a new resource

2018-03-17 Thread Pawan Joshi
Okay, that makes sense. But isn't there a separate "resources" directory
where I can see stuff like branch predictors implemented? I don't have any
br. pred. in my current cpu/o3 directory.
I wanted that as I can get a template to work with.


Pawan
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Re: [gem5-users] Adding a new resource

2018-03-17 Thread Kleovoulos Kalaitzidis
Hello, 
if I clearly understood your question you can do that in the SConscript file in 
the o3 folder. For any new structure you want to add create the equivalent 
files .hh/.cc (and maybe _impl.hh) and make this structure 
compile by including a corespondent line in the SConscript file. And then 
normally use it within the other structures in the pipeline. 
Hope it helps. 

-- 
Kleovoulos Kalaitzidis 
Doctorant - Équipe PACAP 

Centre de recherche INRIA Rennes - Bretagne Atlantique 
Bâtiment 12E, Bureau E321, Campus de Beaulieu, 
35042 Rennes Cedex, France 

- Original Message -

> From: "Pawan Joshi" 
> To: gem5-users@gem5.org
> Sent: Friday, March 16, 2018 6:54:33 PM
> Subject: [gem5-users] Adding a new resource

> Hello all
> I am working on adding a new value predictor structure in the O3 CPU, but
> cannot seem to find the 'resources' directory where I have to code in my
> model. Where will this directory be - src/cpu/o3 doesn't have it.

> Thanks
> Pawan

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Re: [gem5-users] Assertion error in RISCV isa

2018-03-17 Thread Alec Roelke
Great!  I'm glad the patch works for you.  Would you mind leaving a quick
review for it?  All you have to do is click "Reply," click the +1 next to
Code-review, and maybe leave a little comment.

On Sat, Mar 17, 2018 at 2:28 PM, Zaman, Monir 
wrote:

> Quick update.
>
> Applied the patch and ran 445.gobmk again. It is working now.
>
>
>
> Thanks for the patch J
>
>
>
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Re: [gem5-users] Assertion error in RISCV isa

2018-03-17 Thread Zaman, Monir
Quick update.
Applied the patch and ran 445.gobmk again. It is working now.

Thanks for the patch ☺

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Re: [gem5-users] O3CPU DeriveO3CPUParams

2018-03-17 Thread Jason Lowe-Power
Hi Tariq,

You answered your own question :). DerivO3CPU inherits from BaseCPU (just
not directly) in C++ and in Python.

What happens when the SimObject description file is parsed is that a new
C++ class is created. In this case, there is a C++ class called
DerivO3CPUParams. It inherits from BaseCPUParams since the Python SimObject
inherits from BaseCPU.

So, in C++, when you are constructing the DerivO3CPU, you pass the
DerivO3CPU params variable to the super-class (BaseCPU, eventually) which
uses those params as BaseCPUParams.

Cheers,
Jason

On Fri, Mar 16, 2018 at 10:42 AM Tariq Slayer 
wrote:

> Thanks for your reply. I initially thought they were part of variable
> defined in C++ source file, but now it makes sense that these are
> set/changed in python script.
>
> One more thing, inside the O3CPU.py:
>
> class DerivO3CPU(BaseCPU):
> type = 'DerivO3CPU'
> cxx_header = 'cpu/o3/deriv.hh'
>
> The way it is defined is that Deriv03CPU inherits the BaseCPU class.
>
> However in the deriv.hh source, it is written such that:
>
> class DerivO3CPU : public FullO3CPU { ...
>
> which shows the DerivO3CPU inherits the FullO3CPU. Is this ok to define
> this way if they are not matched? I know that FullO3CPU is derived from
> Base03CPU, which is also a child of BaseCPU class.
>
> Thanks
>
> On Fri, Mar 16, 2018 at 11:11 AM, Jason Lowe-Power 
> wrote:
>
>> Hi Tariq,
>>
>> The way SimObject parameters work is explained in Part 2 of Learning gem5
>>  here:
>> http://learning.gem5.org/book/part2/parameters.html. It's a little
>> convoluted (you have to go through python to set parameters), but it is
>> incredibly flexible.
>>
>> The *defaults* for these parameters, specifically, can be found in
>> src/cpu/o3/O3CPU.py. Of course, if you want to change these parameters you
>> should do it in your Python config/run script. The best way is to derive a
>> new class from DerivO3CPU and extend it with your own values for the
>> parameters. Or, if you want to get fancy, you can add command-line
>> parameters for the CPU parameters you want to change dynamically.
>>
>> Cheers,
>> Jason
>>
>> On Fri, Mar 16, 2018 at 9:05 AM Tariq Slayer 
>> wrote:
>>
>>> Hello,
>>>
>>> For O3CPU model, I have question regarding the parameters defined in in
>>> DeriveO3CPU Params. Where are these params being defined? For example in
>>> Fetch.cc source code, some of the arguments in the constructor's parameters
>>> are listed like this:
>>>
>>> ...
>>> decodeToFetchDelay(params->decodeToFetchDelay)
>>> renameToFetchDelay(params->renameToFetchDelay),
>>> iewToFetchDelay(params->iewToFetchDelay)
>>> ...
>>>
>>> For each of these param-> var_name, Where are these variable (or
>>> structure) defined? I know that these params are created in deriv.cc but I
>>> couldn't find the variables listed above. (except for numThread). It is not
>>> listed in BaseCPU class either.
>>>
>>> Also, I know there is a full documentation for InOrder CPU Model, but is
>>> there full doc or tutorial for O3CPU as well? The wiki page of O3CPU looks
>>> partially complete so I was hoping for any documentation that describes all
>>> the pipeline stages and its internal organization inside the O3CPU.
>>>
>>> Thank you
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Re: [gem5-users] Restoring checkpoints with ruby?

2018-03-17 Thread Jason Lowe-Power
Hi Haiyang,

Checkpointing and Ruby hasn't been tested in a while, as far as I know. I
guess what I mean by that is that I haven't used the feature in a long
time, and I don't know of anyone that tracks mainline gem5 that does use
Ruby and checkpointing :).

When taking a checkpoint, you have to use a protocol that implements the
"FLUSH" command. I believe that only MOESI_hammer implements this command.
I could be wrong, though.

Can you checkpoint with MOESI_hammer and restore with MOESI_hammer?

If you're getting deadlocks during restore it's probably a real deadlock.
FIFO ordering violations also seem like something you can't safely ignore.

Are you using the same topology for checkpoint and restore? Ruby uses a
order-specific list to save and restore the controllers. So, if you restore
with a different number of directories, it's possible this perturbs the
controller list so that the L1 caches are in a different place in the list.
This might break restore. It's not very robust.

I would suggest using some debug flags to try to track down the problem
(RubyCacheTrace is the flag you want to print info while restoring, also
possibly ProtocolTrace). You've likely found a bug. If you can track it
down and post a fix to gerrit, we'd appreciate it!

Let me know if you run into any other questions.

Jason

On Fri, Mar 16, 2018 at 1:45 PM Haiyang Han <
haiyang@eecs.northwestern.edu> wrote:

> Hi all,
>
> I'm trying to create and restore checkpoints with ruby while simulating a
> 16-core O3CPU, full system, x86 configuration. I can create the checkpoints
> with no problem, but a little while after restoring from the checkpoints, I
> am seeing all sorts of gem5 aborts due to panics. Sometime it complains
> about a possible deadlock, other times it complains that FIFO ordering is
> violated. Below is the ruby protocols I tried:
>
> *Protocol used to write checkpoint:  Protocol used to restore:*
> MOESI_hammer  MESI_Two_level
> MOESI_hammer  MESI_Three_level
> MESI_Two_level  MESI_Two_level
> MESI_Three_level   MESI_Three_level
>
> I read on http://gem5.org/Checkpoints that only MOESI_hammer supports the
> writing of checkpoints. Does this still apply to the newest gem5 versions?
> Could it be that the traffic generated by the 16 cores is too much for the
> ruby system to handle correctly? Is it possible to solve the deadlock issue
> by manually increasing a threshold somewhere in the source code? What about
> the FIFO ordering violation? It'll be great if any of these are answered :D
>
> Thanks!
> Haiyang
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