Re: [gem5-users] Is classic memory system thread-safe?

[Jason Lowe-Power]

Hi Chen,

To answer your question simply: No.

In almost all cases, gem5 is not thread safe. There are a few very special
circumstances where you can use multiple threads, but you have to be very
careful when doing so.

You can still playback "multithreaded" traces in gem5 by creating multiple
simulated trace CPUs and using a different file for each trace CPU.

Also, to answer your other question, no, the mailing list does not send an
email to the original author by default. I think you can change this
setting in mailman, though.

Jason

---
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Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/



On Thu, May 10, 2018 at 3:12 PM Chen Zou  wrote:

> Hi all,
>
> This is similar to the previous email I sent to the user list, but I made
> some updates.
>
> I am inclined to write my own trace-driver to replay some multi-threaded
> traces on the simulated memory hierarchy (let's say #L1D = #L1I = #L2 =
> #threads_in_the_trace and a shared L3). It seems that L3 could be added
> with a CoherentBus.
>
> If possible, I would like to initiate several threads (say, one pthread
> per thread_in_the_trace) to replay the trace to accelerate the simulation.
> I am worried if the classic cache model is thread-safe, especially if
> there is a shared L3 in the hierarchy. Thanks in advance.
>
> BTW, does the mail-list send the email to the original author? I didn't
> receive my previous email.
>
> Regards,
> Chen
>
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Re: [gem5-users] gem5 cc-NUMA with Ruby

[Jason Lowe-Power]

Hi Heron,

To create a CC-NUMA system with Ruby you should be able to "simply" change
the interconnect latencies in your on-chip network. This can be done by
modifying the python configuration script for the Ruby protocol you are
using.

Unfortunately, the details of the cache hierarchy and the interconnect
topology are confusingly integrated in the python configuration files. You
may find my book's chapter on configuring Ruby helpful:
http://learning.gem5.org/book/part3/simple-MI_example.html

In fact, most Ruby topologies are "NUMA" since there are different paths
from each CPU to the directories (which are the memory controllers).
Specifically, as long as you're not using point-to-point or crossbar it
should be NUMA. However, the built-in topologies are probably not the exact
cache hierarchy/topology that you want to simulate.

Jason

---
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Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/



On Sun, May 6, 2018 at 3:48 AM 张乾龙 <494281...@qq.com> wrote:

> Hi all,
> I'm trying to config cc-NUMA system with RUBY(directory protocol), and
> I searched all the mail-list and read all NUMA related subject and found
> some information helpful but not enouth:
> There are only two subjects about cc-NUMA with RUBY:
> 1. https://www.mail-archive.com/gem5-users@gem5.org/msg06394.html
> Nilay Vaish said maybe coherence should be modified to support cc-NUMA
> 2. https://www.mail-archive.com/gem5-users@gem5.org/msg14942.html
> Jason Lowe-Power  give a hint that using MOESI_CMP_Dir and read the
> "learning_gem5" section
>
> There is one subject about cc-NUMA with CLASSIC memory model, which not
> related and I had already finish this:
> 3. https://www.mail-archive.com/gem5-users@gem5.org/msg09733.html
> Andreas Hansson give some advice on how to config cc-NUMA, but it's
> about CLASSIC memory model in gem5 which only support SNOOPING protocol.
>
> With all those information, I had some questions about config cc-NUMA
> system with RUBY:
> 1. if connect two clusters with "glue" cache in RUBY system, is that
> "glue" cache should be coherent? if it is, the "glue" cache should be
> created by SLICC and the coherence protocol should be modified in *.sm
> files jus as Nilay Vaish said.
> Thanks a lot!
>
> B.R.
> Heron
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Re: [gem5-users] AMD gem5 GPU Compute Model Tutorial at ISCA

[TungHoang_GMail]

Hi Tony,

I knew that AMD has introduced APU + Gem5 as a tutorial of MICRO 2015 (I 
missed change to attend that). Just wondering about the plan to release 
APU as open-source.


/T

On 05/14/2018 08:43 AM, Gutierrez, Anthony wrote:


Hello gem5 Users,

I’d like to announce to you all that we at AMD Research will be 
hosting a tutorial at this year’s ISCA in Los Angeles. The tutorial 
will be half a day and will be held on June 2^nd . The relevant 
details are here:


http://gem5.org/ISCA_2018_Tutorial

If you are interested in learning more about how we model APUs, our SW 
stack, and GPU ISA this is a great way to do so.


We look forward to seeing some of you there.

Thanks,

Tony



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Re: [gem5-users] Understanding how exit event is scheduled

[Jason Lowe-Power]

Hi Utkarsh,

I believe the exit event you are seeing is scheduled by the exit system
call implementation.
https://gem5.googlesource.com/public/gem5/+/master/src/sim/syscall_emul.cc#105

To solve your problem, I would consider how it would be implemented in a
"real" system. Or, if you're simply playing a trace from your new object,
you could ignore the exit event by restarting simulation after the exit
event from your python runscript.

Hope this helps,
Jason

---
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/



On Mon, Apr 30, 2018 at 4:53 AM Utkarsh Singh 
wrote:

> Hi,
>
> As a part of my ongoing project, I am trying to understand how the exit
> event (which is of name and description "Event Event_
> (generic)") is being scheduled in gem5. From what I understand, at the very
> beginning of the simulation (I am running in SE mode) an exit event is
> scheduled at MAX_TICK = 18446744073709551615, and when the benchmark (I am
> using a Hello World executable as a benchmark) finishes execution another
> exit event is scheduled at curTick()+. (I observed this in
> the eventq dump).
>
> Now, what my problem is that I am trying to insert a new component into
> the architecture which reads from a text file, and is connected directly to
> the L3 Bus (I have added an L3 layer to my architecture). However, my
> component will be reading from the text file even after the execution of
> the benchmark is completed. But this isn't happening because the moment the
> benchmark finishes execution an exit event is scheduled because of which
> the simulator stops working.
>
> So I was hoping whether anyone might be able to explain me the mechanism
> of how the exit event gets scheduled, so that I may try to modify the gem5
> code for working things out. I have tried debugging the execution using gdb
> for the past 4 months, but I am unable to understand it due to the
> complexity of the code. I would be really grateful if anyone is able to
> help me out with this problem.
>
> Thank you.
>
> Sincerely,
>
> Utkarsh Singh
> Junior Undergraduate
> Indian Institute of Technology - Delhi
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Re: [gem5-users] Classical vs ruby memory models

[Jason Lowe-Power]

Hello,

See inline answers below.

On Mon, May 14, 2018 at 7:24 AM Sakshi Tiwari 
wrote:

> Can anyone please help me with my queries in the previous mail?
>
> On Sat, May 12, 2018 at 6:34 PM, Sakshi Tiwari 
> wrote:
>
>> Hi,
>>
>> For my work, I had to implement three-levels of caches with LLC as a
>> shared cache. I preferred to extend the classical memory model rather than
>> ruby, because ruby did not support three-level coherence protocol. After
>> modelling L3 cache I further made a lot more changes to the classical
>> memory model.
>>
>> But now I have to extend my work for multi-bank caches, NUCA caches and
>> for a different interconnect, probably NoC.
>>
>> Here are a few questions I have:
>> 1) Is there a way to reuse the implementation of ruby model in classical
>> model?
>>
>
No.


> 2) Is there a code base which has multi-bank caches, NUCA caches and NoC
>> implemented in classical model?
>>
>
No.


> 3) Is it better to switch to ruby model as classical model does not
>> support these implementations?
>>
>
Likely. The classic caches only model a very specific cache organization.
It is a MOESI coherence protocol with a hierarchy of crossbars. If you want
to model anything outside of that organization it will be *very* difficult
to use the classic caches. Ruby is designed to be much more flexible.

You may find my Learning gem5 chapter on Ruby helpful:
http://learning.gem5.org/book/part3/index.html


>
>>
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Re: [gem5-users] Problems with clock() from time.h in x86 32 bit

[Jason Lowe-Power]

Hello,

Have you compiled your binary statically? I believe dynamically linked
executables will only work if the host and the guest are *exactly* the same
(e.g., both x86-64 in this case).

Jason

On Mon, May 14, 2018 at 7:10 AM Øyvind Harboe 
wrote:

> I'm getting a "bad_alloc" from the config/examples/se.py script when I try
> to run the small C application below that calls clock().
>
> Any pointers on what's going on would be most welcome.
>
> Please find a transcript of how I've tested:
>
> I first test with 64 bit, then with 32 bit x86. 64 bit x86 works fine.
>
> $ cd gem5
> $ git describe --tags
> copyright_update-7291-gce00e6042
> $ cat test.c
> #include 
>
> int main(int argc, char **argv)
> {
>   clock();
>   return 0;
> }
> $ gcc ./test.c
> $ build/X86/gem5.opt configs/example/se.py -c ./a.out
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 compiled May 14 2018 14:59:03
> gem5 started May 14 2018 16:00:16
> gem5 executing on davos, pid 31640
> command line: build/X86/gem5.opt configs/example/se.py -c ./a.out
>
> Global frequency set at 1 ticks per second
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (512 Mbytes)
> 0: system.remote_gdb: listening for remote gdb on port 7000
>  REAL SIMULATION 
> info: Entering event queue @ 0.  Starting simulation...
> warn: ignoring syscall access(...)
> warn: ignoring syscall access(...)
> warn: ignoring syscall access(...)
> warn: ignoring syscall mprotect(...)
> warn: ignoring syscall mprotect(...)
> warn: ignoring syscall mprotect(...)
> warn: ignoring syscall mprotect(...)
> Exiting @ tick 91225000 because exiting with last active thread context
>
>
> $ gcc -m32 ./test.c
> $ build/X86/gem5.opt configs/example/se.py -c ./a.out
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 compiled May 14 2018 14:59:03
> gem5 started May 14 2018 16:00:23
> gem5 executing on davos, pid 31648
> command line: build/X86/gem5.opt configs/example/se.py -c ./a.out
>
> Global frequency set at 1 ticks per second
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (512 Mbytes)
> 0: system.remote_gdb: listening for remote gdb on port 7000
>  REAL SIMULATION 
> info: Entering event queue @ 0.  Starting simulation...
> warn: ignoring syscall access(...)
> warn: ignoring syscall access(...)
> warn: ignoring syscall access(...)
> warn: ignoring syscall mprotect(...)
> warn: ignoring syscall mprotect(...)
> warn: ignoring syscall mprotect(...)
> warn: ignoring syscall mprotect(...)
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "/home/oyvind/gem5/src/python/m5/main.py", line 435, in main
> exec filecode in scope
>   File "configs/example/se.py", line 286, in 
> Simulation.run(options, root, system, FutureClass)
>   File "/home/oyvind/gem5/configs/common/Simulation.py", line 712, in run
> exit_event = benchCheckpoints(options, maxtick, cptdir)
>   File "/home/oyvind/gem5/configs/common/Simulation.py", line 268, in
> benchCheckpoints
> exit_event = m5.simulate(maxtick - m5.curTick())
>   File "/home/oyvind/gem5/src/python/m5/simulate.py", line 176, in simulate
> return _m5.event.simulate(*args, **kwargs)
> MemoryError: std::bad_alloc
>
>
>
> --
> Øyvind Harboe, General Manager, Zylin AS, +47 917 86 146
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[gem5-users] AMD gem5 GPU Compute Model Tutorial at ISCA

[Gutierrez, Anthony]

Hello gem5 Users,

I'd like to announce to you all that we at AMD Research will be hosting a 
tutorial at this year's ISCA in Los Angeles. The tutorial will be half a day 
and will be held on June 2nd. The relevant details are here:

http://gem5.org/ISCA_2018_Tutorial

If you are interested in learning more about how we model APUs, our SW stack, 
and GPU ISA this is a great way to do so.

We look forward to seeing some of you there.

Thanks,
Tony
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Re: [gem5-users] gem5 gpu-compute tutorials

[Gutierrez, Anthony]

Hi Chao,

We (AMD) are planning on doing a tutorial at ISCA in Los Angeles on June 2nd. 
Unfortunately that tutorial will cover the latest version of the GPU model, 
which hasn’t been released publicly yet. We plan on releasing our source 
sometime before the tutorial. The model we plan on releasing will be quite 
different from the current GPU model; for example it will now run GCN3 ISA as 
opposed to HSAIL intermediate language and we’ll be supporting the ROCm stack 
instead of OpenCL.

If you cannot attend the tutorial, look for the slides/documentation on the 
wiki sometime in June. I will make an announcement on the mailing list when the 
materials are updated.

For the current HSAIL GPU model we have limited documentation here: 
http://gem5.org/GPU_Models

-Tony

From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Yu Chao
Sent: Friday, May 11, 2018 6:30 PM
To: gem5-users@gem5.org
Subject: [gem5-users] gem5 gpu-compute tutorials

Hi all,


Is there any tutorials on the use of gem5 gpu-compute? I'm going to use the 
gpu-compute in gem5, but i cannot find any tutorials on how to use it.Thanks in 
advance.

Regards,

Chao
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Re: [gem5-users] how to compile hello.c of the linaro image with "Cross-Compile" and execute it in gem5.

[commerce _com]

hi;
yes i compiled hello.c by cross compiler in my ubuntu operating system, and
i copied it in the linaro image but is there a script (- bootscript) to run
the binary hello in fs_fig.LITTLE mode, or how to run it;

thanks;

2018-05-14 15:15 GMT+02:00 조해윤 :

> First, cross compile hello.c. It is not dependent on gem5.
>
> Second, mount the linaro image and copy the binary file.
> For example,
>
> mount -oloop,offset=32256 /tmp/linaro.img /mnt
>
> Finally, run the FS simluation.
> http://gem5.org/Running_gem5
>
>
> 2018-05-13 20:28 GMT+09:00 commerce _com :
>
>> hi all;
>>
>> please help me I am beginner with gem5 ;
>>
>> how to compile hello.c of the linaro image with "Cross-Compile" and
>> execute it in gem5.
>>
>> thanks;
>>
>> ___
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>>
>
>
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Re: [gem5-users] Classical vs ruby memory models

[Sakshi Tiwari]

Can anyone please help me with my queries in the previous mail?

On Sat, May 12, 2018 at 6:34 PM, Sakshi Tiwari 
wrote:

> Hi,
>
> For my work, I had to implement three-levels of caches with LLC as a
> shared cache. I preferred to extend the classical memory model rather than
> ruby, because ruby did not support three-level coherence protocol. After
> modelling L3 cache I further made a lot more changes to the classical
> memory model.
>
> But now I have to extend my work for multi-bank caches, NUCA caches and
> for a different interconnect, probably NoC.
>
> Here are a few questions I have:
> 1) Is there a way to reuse the implementation of ruby model in classical
> model?
> 2) Is there a code base which has multi-bank caches, NUCA caches and NoC
> implemented in classical model?
> 3) Is it better to switch to ruby model as classical model does not
> support these implementations?
>
>
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[gem5-users] Problems with clock() from time.h in x86 32 bit

[Øyvind Harboe]

I'm getting a "bad_alloc" from the config/examples/se.py script when I try
to run the small C application below that calls clock().

Any pointers on what's going on would be most welcome.

Please find a transcript of how I've tested:

I first test with 64 bit, then with 32 bit x86. 64 bit x86 works fine.

$ cd gem5
$ git describe --tags
copyright_update-7291-gce00e6042
$ cat test.c
#include 

int main(int argc, char **argv)
{
  clock();
  return 0;
}
$ gcc ./test.c
$ build/X86/gem5.opt configs/example/se.py -c ./a.out
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled May 14 2018 14:59:03
gem5 started May 14 2018 16:00:16
gem5 executing on davos, pid 31640
command line: build/X86/gem5.opt configs/example/se.py -c ./a.out

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
Exiting @ tick 91225000 because exiting with last active thread context


$ gcc -m32 ./test.c
$ build/X86/gem5.opt configs/example/se.py -c ./a.out
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled May 14 2018 14:59:03
gem5 started May 14 2018 16:00:23
gem5 executing on davos, pid 31648
command line: build/X86/gem5.opt configs/example/se.py -c ./a.out

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
Traceback (most recent call last):
  File "", line 1, in 
  File "/home/oyvind/gem5/src/python/m5/main.py", line 435, in main
exec filecode in scope
  File "configs/example/se.py", line 286, in 
Simulation.run(options, root, system, FutureClass)
  File "/home/oyvind/gem5/configs/common/Simulation.py", line 712, in run
exit_event = benchCheckpoints(options, maxtick, cptdir)
  File "/home/oyvind/gem5/configs/common/Simulation.py", line 268, in
benchCheckpoints
exit_event = m5.simulate(maxtick - m5.curTick())
  File "/home/oyvind/gem5/src/python/m5/simulate.py", line 176, in simulate
return _m5.event.simulate(*args, **kwargs)
MemoryError: std::bad_alloc



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Re: [gem5-users] how to compile hello.c of the linaro image with "Cross-Compile" and execute it in gem5.

[조해윤]

First, cross compile hello.c. It is not dependent on gem5.

Second, mount the linaro image and copy the binary file.
For example,

mount -oloop,offset=32256 /tmp/linaro.img /mnt

Finally, run the FS simluation.
http://gem5.org/Running_gem5


2018-05-13 20:28 GMT+09:00 commerce _com :

> hi all;
>
> please help me I am beginner with gem5 ;
>
> how to compile hello.c of the linaro image with "Cross-Compile" and
> execute it in gem5.
>
> thanks;
>
> ___
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