[gem5-users] Response for WritebackDirty packets (learning.gem5)
Hello All, Following jason's website, created my own cache. On Cache miss, I send the TimingReq to memory, and get the response, which I handle in "handleResponse". during HandleResponse, in case the insertion causes eviction (cache was full), the insert function generates another memPort.sendTimingReq(). This time, the pkt is WritebackDirty. However, For this TimingReq() to memory (WritebackDirty), we don't get any response from memory Write? My question is: Do we ever get a response from memory for packets of type "WritebackDirty". When I examine the simulator output, it seems that it moves on to next instrutions without waiting for response from memory for this particular request. Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] the instructions that are responsible for the number of access to the cache and energy consumption.
Hi all; I need to do an analysis on the change of time of execution of a parsec 3.0 application (ex: blackscholes) in gem5 and I do not know the statistics (the instructions of file stats.txt) which are responsbales on the change of execution time (for example the instructions that are responsible for the number of access to the cache, energy consumption ... etc) please if you have an idea help me. Thanks advance; ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Issues in handling compressed data for L3 cache
Hi friends, I have been implementing Cache Compression algorithm in gem5. So in order to tap data for all the writes into L3 cache I have been using handleFill() function in cache.cc file. I have been using following command to transfer data in compressed format into L3 cache. ---*Code snippet*- //Only for L3 cache uint8_t *dataofCacheLine; memcpy(dataOfCacheLine, pkt->getConstPtr(), blkSize); compr_Info = compressionAlgo (dataOfCacheLine, ., .); //compr_Info contains compressed data and new size. //compressed data is then transferred into blk->data in the following way memcpy(blk->data, compr_info.comprData, compr_info.comprSize); Doing this leads to SIGABRT signal which terminates the execution with a panic ("Tried to read unmapped address 0x1a8"). I debugged it with gdb and log files and got myself zero'd down to error in memcpy statement. Could any of you let me know why there is a crash due to second memcpy statement provided compressed data I am storing is consistent with the actual data referenced by the block? Does any addressing gets disturbed when I am doing it like this? If Yes, could you please give me some inputs on this?? Thanks a lot in advance! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users