Your logic sounds correct to me for single core.
For multi core, the last level cache is shared, and you can get block from
other core’s L1 dcache.
So you need to think through about what behavior you are expecting from
your design and make changes or keep things same.
On Mon, May 13, 2019 at 12:
Dear Abhishek,
Many thanks for your reply. I will set the flag in response packet for
L2 hit. This flag will be default reset, therefore, I think I will not need
main memory flag in this case.
Please, let me know if you feel a problem in this logic.
For multicore simulation, what sh
Hello Nazish,
If you are using classic memory, edit src/mem/cache/base.cc file’s
recvTimingReq function.
You can access the old data through blk->data and the new data by
pkt->getdata(this you need to search in src/mem/packet.hh, I may have made
mistake in writing correct name of the function).
O
