Re: [gem5-users] Linux boot

[Abhishek Singh]

Hi Yuan,

The way I simulate DerivO3CPU, (first run)is I run with AtomicSimpleCPU and
create a checkpoint after the boot by using command “/sbin/m5 checkpoint”
and then run the benchmark.

In my second run I restore checkpoint using AtomicSimpleCPU and then switch
to DerivO3CPU.

And then I get the final stats using DerivO3CPU.



On Thu, Feb 27, 2020 at 1:13 AM Shougang Yuan  wrote:

> Hi, Abhishek,
>
> I also have similar questions. I can boot the ubuntu18.04 and kernel 5.2.3
> with timingSimpleCPu and KVM, but I want to run simulation with
> DeriveO3CPU. Do you know how to change the CPU to DeriveO3 after we boot
> the system with kvm or timingsimple cou?
>
> Best regards.
>
> Yuan
>
> On Thu, Feb 27, 2020 at 1:10 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>>
>> Hi,
>>
>> You can use KVM CPU, it will boot the system fast as it works on host
>> machine speed.
>>
>> On Thu, Feb 27, 2020 at 1:00 AM niranjan soundararajan <
>> niranja...@gmail.com> wrote:
>>
>>> Hello
>>>
>>> We are booting Ubuntu 18.0.4 and kernel 5.2.3 on x86_64 bit core. We are
>>> running the following commandline
>>>
>>> ./build/X86/gem5.opt configs/example/fs.py
>>> --disk-image=ubuntu_base_v1.1.img --kernel=vmlinux-5.2.3
>>> --cpu-type=AtomicSimpleCPU --caches --l2cache --mem-size=8192MB
>>>
>>> We notice that the boot process starts and proceeds successfully until
>>> we hit the following point (see below). Its stuck there for quite some
>>> time. I wanted to check if this is common or is there something we can do
>>> to speed it up? Whats sort of the typical boot times folks have seen with
>>> x86 cores (or others) and is there a checkpoint we can take in case we run
>>> into errors to avoid starting from scratch?
>>>
>>> *[  OK  ] Reached target Remote File Systems.*
>>>
>>> * Starting Availability of block devices...*
>>>
>>> *[  OK  ] Started Availability of block devices.*
>>>
>>>
>>>
>>> Thanks
>>>
>>> Niranjan
>>> ___
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>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
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Re: [gem5-users] Linux boot

[Shougang Yuan]

Hi, Abhishek,

I also have similar questions. I can boot the ubuntu18.04 and kernel 5.2.3
with timingSimpleCPu and KVM, but I want to run simulation with
DeriveO3CPU. Do you know how to change the CPU to DeriveO3 after we boot
the system with kvm or timingsimple cou?

Best regards.

Yuan

On Thu, Feb 27, 2020 at 1:10 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

>
> Hi,
>
> You can use KVM CPU, it will boot the system fast as it works on host
> machine speed.
>
> On Thu, Feb 27, 2020 at 1:00 AM niranjan soundararajan <
> niranja...@gmail.com> wrote:
>
>> Hello
>>
>> We are booting Ubuntu 18.0.4 and kernel 5.2.3 on x86_64 bit core. We are
>> running the following commandline
>>
>> ./build/X86/gem5.opt configs/example/fs.py
>> --disk-image=ubuntu_base_v1.1.img --kernel=vmlinux-5.2.3
>> --cpu-type=AtomicSimpleCPU --caches --l2cache --mem-size=8192MB
>>
>> We notice that the boot process starts and proceeds successfully until we
>> hit the following point (see below). Its stuck there for quite some time. I
>> wanted to check if this is common or is there something we can do to speed
>> it up? Whats sort of the typical boot times folks have seen with x86 cores
>> (or others) and is there a checkpoint we can take in case we run into
>> errors to avoid starting from scratch?
>>
>> *[  OK  ] Reached target Remote File Systems.*
>>
>> * Starting Availability of block devices...*
>>
>> *[  OK  ] Started Availability of block devices.*
>>
>>
>>
>> Thanks
>>
>> Niranjan
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Re: [gem5-users] Linux boot

[Abhishek Singh]

Hi,

You can use KVM CPU, it will boot the system fast as it works on host
machine speed.

On Thu, Feb 27, 2020 at 1:00 AM niranjan soundararajan 
wrote:

> Hello
>
> We are booting Ubuntu 18.0.4 and kernel 5.2.3 on x86_64 bit core. We are
> running the following commandline
>
> ./build/X86/gem5.opt configs/example/fs.py
> --disk-image=ubuntu_base_v1.1.img --kernel=vmlinux-5.2.3
> --cpu-type=AtomicSimpleCPU --caches --l2cache --mem-size=8192MB
>
> We notice that the boot process starts and proceeds successfully until we
> hit the following point (see below). Its stuck there for quite some time. I
> wanted to check if this is common or is there something we can do to speed
> it up? Whats sort of the typical boot times folks have seen with x86 cores
> (or others) and is there a checkpoint we can take in case we run into
> errors to avoid starting from scratch?
>
> *[  OK  ] Reached target Remote File Systems.*
>
> * Starting Availability of block devices...*
>
> *[  OK  ] Started Availability of block devices.*
>
>
>
> Thanks
>
> Niranjan
> ___
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[gem5-users] Linux boot

[niranjan soundararajan]

Hello

We are booting Ubuntu 18.0.4 and kernel 5.2.3 on x86_64 bit core. We are
running the following commandline

./build/X86/gem5.opt configs/example/fs.py
--disk-image=ubuntu_base_v1.1.img --kernel=vmlinux-5.2.3
--cpu-type=AtomicSimpleCPU --caches --l2cache --mem-size=8192MB

We notice that the boot process starts and proceeds successfully until we
hit the following point (see below). Its stuck there for quite some time. I
wanted to check if this is common or is there something we can do to speed
it up? Whats sort of the typical boot times folks have seen with x86 cores
(or others) and is there a checkpoint we can take in case we run into
errors to avoid starting from scratch?

*[  OK  ] Reached target Remote File Systems.*

* Starting Availability of block devices...*

*[  OK  ] Started Availability of block devices.*



Thanks

Niranjan
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Re: [gem5-users] Kernel for x64

[niranjan soundararajan]

Thanks, will check it out

On Wed, Feb 26, 2020 at 12:48 PM Muhammet Abdullah Soytürk <
muhammetabdullahsoyt...@gmail.com> wrote:

> Hi Niranjan,
>
> You can check this
> 
> tutorial to see which kernels are booting successfully.
>
> Best,
> Muhammet
>
> niranjan soundararajan , 26 Şub 2020 Çar, 09:31
> tarihinde şunu yazdı:
>
>> Hello
>>
>> Has anyone got a recent Linux kernel (Ubuntu 18.0.4) for GEM5 working for
>> x64 (x86 64 bit)? We are running into the following issues (when trying
>> different kernel versions)
>>
>> 1. panic condition !pci_dev occurred: 00:01.4: Write to config space on
>> non-existent PCI device
>>
>> 2. VFS: Cannot open root device "hda1" or unknown-block(0,0)
>>
>>
>> Thanks
>> Niranjan
>>
>> ___
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>
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Re: [gem5-users] ARM SPI interrupt 1 to N model support

[HENG ZHUO]

Hi Giacomo,

Thanks for the information, that is very useful information to know and make 
perfect sense on how to route to specific cpu.

Just to clarify, I guess the question should be phrased as they are handled by 
same cpu(determined by the affinity numbers)? Then, lets say in some cases, I 
want to distribute the interrupts across group of cpus, so who ever is free(or 
round robin, any algorithm) read the interrupt, doing that will not be possible 
now?

>From my understanding, this will be in hardware level, software can not help 
>with this. Correction me if I am wrong.

Thanks for the help!

Best,
Heng

On Feb 26, 2020, at 04:45, Giacomo Travaglini 
mailto:giacomo.travagl...@arm.com>> wrote:

Hi Heng,

Even if we don't support 1 to N model in gem5, it is not strictly true that all 
SPIs are handled by cpu0.
In fact this is managed at software level.

SPIs are handled at the Distributor level (GICD): All SPIs (from 32 to 1019) 
have a personal GICD_IROUTER
register selecting to which the PE (cpu) the interrupt will be routed by the 
GIC.

https://developer.arm.com/docs/ddi0601/b/external-system-registers/gicd_irouterne

The register has a set of fields (Affinity numbers) tagging a PE in your 
cluster configuration.
In gem5 core0 will have an affinity value of 0.0.0.0; core1 will have 0.0.0.1
(Anyway have a look at the MPIDR register value in the arm reference manual for 
more info)

So if you want to deliver an interrupt to core1 you should write 0.0.0.1 to the 
specific GICD_IROUTER register.

How can you do that?

I have never tested it, but I think this is doable via the procfs:

Change the value of:

/proc/irq//smp_affinity

and double check if this constitutes a write to IROUTER.
Then test the interrupt and let us know if it worked.

if you read /proc/interrupts, it should tell you to which CPU an interrupt has 
been delivered

Regards

Giacomo











From: gem5-users 
mailto:gem5-users-boun...@gem5.org>> on behalf of 
HENG ZHUO mailto:hzh...@wisc.edu>>
Sent: 25 February 2020 21:15
To: gem5-users@gem5.org 
mailto:gem5-users@gem5.org>>
Subject: [gem5-users] ARM SPI interrupt 1 to N model support

Dear all,

I noticed that in ARM multi core fs simulation, SPI (shared processor 
interrupts, Ethernet interrupt for instance) is all handled by cpu0. I was 
looking for mechanisms letting all cpu involved in handling interrupts.

After some literature research and code digging, seems like 1-N (in gic v2) or 
1 of N (in gic v3) features is not supported. Am I missing something here or is 
this actually some features that are not supported now?

Any help is appreciated! Thanks.

Best,
Heng

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Re: [gem5-users] ARM SPI interrupt 1 to N model support

[Giacomo Travaglini]

Hi Heng,

Even if we don't support 1 to N model in gem5, it is not strictly true that all 
SPIs are handled by cpu0.
In fact this is managed at software level.

SPIs are handled at the Distributor level (GICD): All SPIs (from 32 to 1019) 
have a personal GICD_IROUTER
register selecting to which the PE (cpu) the interrupt will be routed by the 
GIC.

https://developer.arm.com/docs/ddi0601/b/external-system-registers/gicd_irouterne

The register has a set of fields (Affinity numbers) tagging a PE in your 
cluster configuration.
In gem5 core0 will have an affinity value of 0.0.0.0; core1 will have 0.0.0.1
(Anyway have a look at the MPIDR register value in the arm reference manual for 
more info)

So if you want to deliver an interrupt to core1 you should write 0.0.0.1 to the 
specific GICD_IROUTER register.

How can you do that?

I have never tested it, but I think this is doable via the procfs:

Change the value of:

/proc/irq//smp_affinity

and double check if this constitutes a write to IROUTER.
Then test the interrupt and let us know if it worked.

if you read /proc/interrupts, it should tell you to which CPU an interrupt has 
been delivered

Regards

Giacomo











From: gem5-users  on behalf of HENG ZHUO 

Sent: 25 February 2020 21:15
To: gem5-users@gem5.org 
Subject: [gem5-users] ARM SPI interrupt 1 to N model support

Dear all,

I noticed that in ARM multi core fs simulation, SPI (shared processor 
interrupts, Ethernet interrupt for instance) is all handled by cpu0. I was 
looking for mechanisms letting all cpu involved in handling interrupts.

After some literature research and code digging, seems like 1-N (in gic v2) or 
1 of N (in gic v3) features is not supported. Am I missing something here or is 
this actually some features that are not supported now?

Any help is appreciated! Thanks.

Best,
Heng

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Re: [gem5-users] Kernel for x64

[Ciro Santilli]

And this is a Buildroot setup tested on ARM and X86:
https://github.com/cirosantilli/linux-kernel-module-cheat#gem5-buildroot-setup-getting-started

On Wed, Feb 26, 2020 at 6:31 AM niranjan soundararajan
 wrote:
>
> Hello
>
> Has anyone got a recent Linux kernel (Ubuntu 18.0.4) for GEM5 working for x64 
> (x86 64 bit)? We are running into the following issues (when trying different 
> kernel versions)
>
> 1. panic condition !pci_dev occurred: 00:01.4: Write to config space on 
> non-existent PCI device
>
> 2. VFS: Cannot open root device "hda1" or unknown-block(0,0)
>
>
> Thanks
> Niranjan
>
> ___
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