[gem5-users] Re: Memory Addresses in Gem5

[ABD ALRHMAN ABO ALKHEEL via gem5-users]

Hi,

Thank you for your email.

Do you have any idea how to construct a packet with a request to read from the 
memory address? For instance, let us assume that the address that I want to 
read the data from it is (0x2345),  I want to read the 256 bytes of this 
address (0x2300-0x23ff)? I want to do that for debugging like this 
https://www.gem5.org/_pages/static/scripts/part2/memoryobject/simple_memobj.cc.

Any help would be appreciated.

Thanks


From: Ahmed, Md Rubel via gem5-users 
Sent: Wednesday, August 12, 2020 12:44 AM
To: gem5 users mailing list 
Cc: Ahmed, Md Rubel 
Subject: [gem5-users] Re: Memory Addresses in Gem5

Hi,

pkt->getAddr()  returns memory address. pkt->print() also returns block address 
and offset.

Thanks

From: ABD ALRHMAN ABO ALKHEEL via gem5-users 
Sent: Tuesday, August 11, 2020 6:32 PM
To: gem5 users mailing list ; gem5-users 

Cc: ABD ALRHMAN ABO ALKHEEL 
Subject: [gem5-users] Memory Addresses in Gem5

Hi All,

Does the packet in gem5 have the memory address? for example, does this 
pkt->getAddr() return the memory address or not? If so, is that address 
physical or virtual?

Thanks

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[gem5-users] Re: Memory Addresses in Gem5

[Ahmed, Md Rubel via gem5-users]

Hi,

pkt->getAddr()  returns memory address. pkt->print() also returns block address 
and offset.

Thanks

From: ABD ALRHMAN ABO ALKHEEL via gem5-users 
Sent: Tuesday, August 11, 2020 6:32 PM
To: gem5 users mailing list ; gem5-users 

Cc: ABD ALRHMAN ABO ALKHEEL 
Subject: [gem5-users] Memory Addresses in Gem5

Hi All,

Does the packet in gem5 have the memory address? for example, does this 
pkt->getAddr() return the memory address or not? If so, is that address 
physical or virtual?

Thanks

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sender and know the content is safe.
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[gem5-users] Memory Addresses in Gem5

[ABD ALRHMAN ABO ALKHEEL via gem5-users]

Hi All,

Does the packet in gem5 have the memory address? for example, does this 
pkt->getAddr() return the memory address or not? If so, is that address 
physical or virtual?

Thanks
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[gem5-users] Modifying MinorCPU to be slightly out of order for some memory instructions

[Muhammad Aamir via gem5-users]

Hi everyone,

I have been modifying the MinorCPU to be like an out of order CPU for
certain memory instructions. My modification involved this "instructions"
to not stall the pipeline and allow the cpu to continue processing other
instructions.

Coming to the problem that I am facing is that when i remove this "memory
access instructions" from the inFlightInsts queue,(I remove them from
inFlightInstsqueue after sending them to my custom made LSQ) is that I do
not see a reduce in number of ticks it takes to execute the guest code.
(i.e. it takes the same time similar to the one where i do not remove this
instructions). Which according to my opinion should be faster as the memory
instructions have been removed from the inFlightQueue.

On further investigation, I found out this is because
of thread->getDTBPtr()->translateTiming in the lsq.cc file.  It adds up the
number of ticks of the memory instruction even though the instruction no
longer resides in the inFlightInsts Queue.

My question is why is GEM5 still adding additional ticks when accessing the
translateTiming function though it is working in the background and not
stalling the instruction pipeline. Should it not consider this ticks as
that instruction is no longer in the inFlightInsts queue?

Also, is there a way I can fix this so that it doesn't add upto the final
count of ticks for those instructions?

Any help would be appreciated.

Thanks,
Muhammad Aamir Saeed
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[gem5-users] Re: Error only occurs with higher number of clusters and cpus

[Ciro Santilli via gem5-users]

We have to understand the root cause to be sure, it often happens that memory 
errors are just hidden by random changes. Let's move all discussion to that 
ticket. I've started dumping some logs for it and linked to the ticket BTW.

From: Sebastian Block 
Sent: Tuesday, August 11, 2020 11:37 AM
To: gem5-users@gem5.org ; Ciro Santilli 

Cc: nd 
Subject: Re: [gem5-users] Error only occurs with higher number of clusters and 
cpus

The error seems to relate to the kernel used. I build a new kernel (gem5: 
Building ARM 
Kernel)
 and now I'm able to simulate even more cpus. The kernel i used is the v4.14 
version.


Am Freitag, 7. August 2020, 20:08:10 MESZ hat Sebastian Block 
 Folgendes geschrieben:



Thank you very much. I will give Ruby a try.
Am Freitag, 7. August 2020, 16:41:12 MESZ hat Ciro Santilli 
 Folgendes geschrieben:


It might be the same as: https://gem5.atlassian.net/browse/GEM5-711 I want to 
investigate that soon hopefully.

If you try Ruby and it fails, please open a separate bug, we want it to work as 
well 🙂

From: Sebastian Block via gem5-users 
Sent: Friday, August 7, 2020 9:27 AM
To: gem5-users@gem5.org 
Cc: Sebastian Block 
Subject: [gem5-users] Error only occurs with higher number of clusters and cpus

Hi all,

My gem5 project consists of clusters and some cpus in the clusters, simulating 
them in fs mode.
Simulating in atomic mode always works.
While simulating less then 6 cpus works perfectly fine in timing mode, with 
more then 6 the simulation crashes with the error:

panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && 
!pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq 
[80a70800:80a70803] UC where needsWritable, does not match isInvalidate
Memory Usage: 9072952 KBytes
Program aborted at tick 175141645000
--- BEGIN LIBC BACKTRACE ---

At the moment the project uses classic caches. Private L1 and shared L2 caches. 
I didn't test it with L3 caches as the simulation crashes sometimes.
Is it possible that the error occurs because of the classic caches and cache 
coherence?
Might the error vanish when using Ruby?
An L3 cache should also be implemented. Is it difficult to do that in Ruby?

Thank you very much for your help.

Best regards
Sebastian

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[gem5-users] posting

[masi suji via gem5-users]

my emailid is sujim...@gmail.com

regards
sujatha
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[gem5-users] Re: Error only occurs with higher number of clusters and cpus

[Sebastian Block via gem5-users]

 The error seems to relate to the kernel used. I build a new kernel (gem5: 
Building ARM Kernel) and now I'm able to simulate even more cpus. The kernel i 
used is the v4.14 version.

Am Freitag, 7. August 2020, 20:08:10 MESZ hat Sebastian Block 
 Folgendes geschrieben:  
 
  
Thank you very much. I will give Ruby a try.Am Freitag, 7. August 2020, 
16:41:12 MESZ hat Ciro Santilli  Folgendes geschrieben:  
 
 #yiv4237158419 P {margin-top:0;margin-bottom:0;}It might be the same as: 
https://gem5.atlassian.net/browse/GEM5-711 I want to investigate that soon 
hopefully.
If you try Ruby and it fails, please open a separate bug, we want it to work as 
well🙂From: Sebastian Block via gem5-users 
Sent: Friday, August 7, 2020 9:27 AM
To: gem5-users@gem5.org 
Cc: Sebastian Block 
Subject: [gem5-users] Error only occurs with higher number of clusters and cpus 
Hi all,
My gem5 project consists of clusters and some cpus in the clusters, simulating 
them in fs mode.Simulating in atomic mode always works. While simulating less 
then 6 cpus works perfectly fine in timing mode, with more then 6 the 
simulation crashes with the error: 
panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && 
!pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq 
[80a70800:80a70803] UC where needsWritable, does not match isInvalidateMemory 
Usage: 9072952 KBytesProgram aborted at tick 175141645000--- BEGIN LIBC 
BACKTRACE ---At the moment the project uses classic caches. Private L1 and 
shared L2 caches. I didn't test it with L3 caches as the simulation crashes 
sometimes.Is it possible that the error occurs because of the classic caches 
and cache coherence?Might the error vanish when using Ruby? An L3 cache should 
also be implemented. Is it difficult to do that in Ruby?
Thank you very much for your help.
Best regardsSebastian
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