[gem5-users] Adjusting gem5 CPU simulation granularity in heterogeneous memory environments?

Dear gem5 developers/users, In order to study memory management techniques in heterogenous memory environments we have been working on extending gem5 to handle multiple memory devices (i.e., NUMA). We would like to decrease the time spent on simulating CPU internals without losing accuracy on

[gem5-users] FLUSH request from CPU sequencer to cache controller

Hi all, I am running PARSEC benchmark with full system simulation. The CPU model is O3CPU (parameters tuned) with ARM ISA and MESI_Three_Level protocol were used. (build/ARM_MESI_Three_Level/gem5.opt) While the benchmark is running, panic occurs since the L0 cache controller gets unsupported type

[gem5-users] Hi gem5 users

lucky19...@iiitd.ac.in Regards, *Lucky Agarwal* ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: Question about MESI_Three_Level protocol

Hi Daecheol, You're correct that MESI_Three_Level, like MESI_Two_Level has a shared (banked) LLC. The L2 cache is chosen based on the function "mapAddressToRange" (see https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm#403 ). The

[gem5-users] Question about MESI_Three_Level protocol

Hi all, I am making a system consisting of multiple CPU clusters using MESI_Three_Level. Since the MESI three level enable users to make multiple clusters, and each cluster can have multiple L2 caches, I just thought that L1 caches within the cluster can only access the L2 cache in the same