Hi All:
I use gem5 20.1 ,and bootup with fs.py and dramsim3 model,but some
error printed.
As I know, gem5 20.1 new feature has departed the medium interface
from memctrl, however, these modifications are only for the DRAM model inside
gem5, I think external memory Dramsim3
Hi everyone:
I have ran a C language benchmark containing SVE intrinsics in gem5. When I
adapt the different SVE vector bit width in se mode, I will get some
performance improvement. However, the performance changed hardly in fs mode,
even irregular. I wonder why ithappens?The following is the
Hello Jason:
I defined the following transitions when flushing is executed in the I state, I
did not use ruby_random_test.py to test at first, but created checkpoint in SE
mode, and no error was reported, printed information shows flush_line I->I.
But when I execute the following command line,
Thank's your reply,bobby.
I am confused at how I can know which level the cache is working.when debugging
gem5,The packet was transmit from one port to another,but the port belong to
which Cache,L1 or L2? (For example, after L1 MISS, look for data in L2 ).Best
wish.
Hi Ayaz,
I can't thank you enough for you reply. I'm aware of the fact that from
software's perspective, VIPT and PIPT should be functioning equally but what
piqued my interest is what it looks like from hardware's perspective.
Let's say both i-cache and d-cache are working under PIPT, do you
Hi Leon,
In gem5, the caches are PIPT technically. But, you can model the timing of
a VIPT cache by changing the latency of your cache. As far as the kernel
boot log is concerned, I am not fully sure if "CPU: PIPT / VIPT nonaliasing
data cache, PIPT instruction cache" refers to the actual
Hey,
I'm not sure I understand exactly what you're asking. I assume you're
learning from the "learning gem5" tutorial (here :
http://www.gem5.org/documentation/learning_gem5/introduction/)? If so,
could you point us towards the exact part that's confusing you?
Kind regards,
Bobby
--
Dr. Bobby
Hello,
It depends on how you want to model banking. If you just want to set and
limit the bandwidth to a cache, you can use the "resourceStalls = true"
option on the RubyCache object and set the tag and data array values. You
will also have to tag every transition in the cache controller (i.e.,
Hello,
It's difficult for me to say for certain without digging much deeper.
However, my gut says the latter is probably closer to correct. I doubt that
you can drop the line without first receiving an ack (somehow).
I'm not sure if this was said before, but you can use the Ruby random
tester in
Hi Tracy,
The example of PARSEC benchmark mentioned in the documentation page
can be found here,
https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations
Regards,
Hoa Nguyen
On 10/13/20, Tracy Mac via gem5-users wrote:
> Hi ALL!
>
> I try to run spec2006 in gem5 full system mode
Hi All:
How to modify the storage device driver,virtio_blk? As I know, the
device name using fs.py is /dev/sda1.
Because I have met a error using fs_bigLITTLE.py when I restore from
checkpoint, the below print in system.terminal accured, and fs.py will never
accur.(I have
When debugging gem5, I want to know what microops are in the reorder buffer,
instruction queue or decoding queue? Is there any way to do it? When debugging
with gdb, when I use p queuename, the display is similar to
{std::queue wrapping: std::deque with 8 elements = {{data = 0x23e5d700}, {data
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