[gem5-users] Re: Copying/Writing data from one packet to another packet in gem5

[Ayaz Akram via gem5-users]

Hi Aritra,

As you might have already noticed that there is a ptr to the data being
transferred (PacketDataPtr data) in the packet class:

http://doxygen.gem5.org/release/current/classPacket.html

I think you should be able to use methods like setData(), writeData() from
the same class to copy data from one packet to the other using a ptr to
that data.

-Ayaz

On Fri, Apr 9, 2021 at 12:42 PM bagchi95aritra--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> In gem5, the data a packet brings from the main memory to the cache is
> first written into a particular cache block. Later, that cache block
> supplies the data to the outstanding misses at the MSHR (targets). gem5 has
> some built-in methods defined under the “Packet” class for transferring
> data between a cache block and a packet.
>
> Is there any way/method in gem5 by which the data of a packet can directly
> be written/copied to another packet? Can anyone put some light on it?
>
> Thanks and regards,
> Aritra
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[gem5-users] Re: FS RISCV PCI

[Ayaz Akram via gem5-users]

Hi Nikolaos,

Thanks for bringing this to our attention. We are looking at this problem
here at Davis and will try to respond soon.

-Ayaz

On Sat, Apr 10, 2021 at 4:42 AM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:

>
> Dear Gem5 community,
>
> I try to add PCI interface in RISCV arch doing the following steps
> (similar with ARM RealView - I use the gem5-v21):
>
> 1) Create a file gem5/src/dev/riscv/pci_host.cc with the following code:
>
> #include "dev/riscv/pci_host.hh"
> #include "params/GenericRiscvPciHost.hh"
>
> GenericRiscvPciHost::GenericRiscvPciHost(const GenericRiscvPciHostParams
> &p)
>  : GenericPciHost(p), intBase(p.int_base), intCount(p.int_count)
> {
> }
>
> uint32_t
> GenericRiscvPciHost::mapPciInterrupt(
>  const PciBusAddr &addr, PciIntPin pin) const
> {
>
>  fatal_if(pin == PciIntPin::NO_INT,
>   "%02x:%02x.%i: Interrupt from a device without interrupts\n",
>   addr.bus, addr.dev, addr.func);
>
>  return intBase + (addr.dev % intCount);
> }
>
> 2) Create a file gem5/src/dev/riscv/pci_host.hh with the following code:
>
> #ifndef __DEV_RISCV_PCI_HOST_HH__
> #define __DEV_RISCV_PCI_HOST_HH__
>
> #include "dev/pci/host.hh"
>
> struct GenericRiscvPciHostParams;
>
> class GenericRiscvPciHost : public GenericPciHost
> {
>private:
>  const uint32_t intBase;
>  const uint32_t intCount;
>
>public:
>  GenericRiscvPciHost(const GenericRiscvPciHostParams &p);
>  virtual ~GenericRiscvPciHost() {}
>
>protected:
>  uint32_t mapPciInterrupt(const PciBusAddr &addr,
>   PciIntPin pin) const override;
> };
>
> #endif // __DEV_RISCV_PCI_HOST_HH__
>
> 3) Add the "Source('pci_host.cc')" to gem5/src/dev/riscv/SConscript
>
> 4) Add the following code in gem5/src/dev/riscv/HiFive.py according to
> RealView GenericArmPciHost:
>
> from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000
>
> from m5.objects.Device import BasicPioDevice
> from m5.objects.PciHost import *
> from m5.SimObject import SimObject
>
> class GenericRiscvPciHost(GenericPciHost): #Add this class (PCI)
>  type = 'GenericRiscvPciHost'
>  cxx_header = "dev/riscv/pci_host.hh"
>  int_base   = Param.Unsigned("PCI interrupt base")
>  int_count  = Param.Unsigned("Maximum number of interrupts used by
> this host")
>
>  # This python parameter can be used in configuration scripts to turn
>  # on/off the fdt dma-coherent flag when doing dtb autogeneration
>  _dma_coherent = True
>
>  def generateDeviceTree(self, state):
>  local_state = FdtState(
>  addr_cells=3, size_cells=2,
>  cpu_cells=1, interrupt_cells=1)
>
>  node = FdtNode("pci")
>
>  if int(self.conf_device_bits) == 8:
>  node.appendCompatible("pci-host-cam-generic")
>  elif int(self.conf_device_bits) == 12:
>  node.appendCompatible("pci-host-ecam-generic")
>  else:
>  m5.fatal("No compatibility string for the set
> conf_device_width")
>
>  node.append(FdtPropertyStrings("device_type", ["pci"]))
>
>  # Cell sizes of child nodes/peripherals
>  node.append(local_state.addrCellsProperty())
>  node.append(local_state.sizeCellsProperty())
>  node.append(local_state.interruptCellsProperty())
>  # PCI address for CPU
>  node.append(FdtPropertyWords("reg",
>  state.addrCells(self.conf_base) +
>  state.sizeCells(self.conf_size) ))
>
>  # Ranges mapping
>  # For now some of this is hard coded, because the PCI module does
> not
>  # have a proper full understanding of the memory map, but
> adapting the
>  # PCI module is beyond the scope of what I'm trying to do here.
>  # Values are taken from the VExpress_GEM5_V1 platform.
>  ranges = []
>  # Pio address range
>  ranges += self.pciFdtAddr(space=1, addr=0)
>  ranges += state.addrCells(self.pci_pio_base)
>  ranges += local_state.sizeCells(0x1)  # Fixed size
>
>  # AXI memory address range
>  ranges += self.pciFdtAddr(space=2, addr=0)
>  ranges += state.addrCells(self.pci_mem_base)
>  ranges += local_state.sizeCells(0x4000) # Fixed size
>  node.append(FdtPropertyWords("ranges", ranges))
>
>  if True:
>#Change this to True because Realview calls always
> ARM_PCI_INT_DEV
>  plic = self._parent.unproxy(self).plic
>  int_phandle = state.phandle(plic)
>  # Interrupt mapping
>  interrupts = []
>
>  # child interrupt specifier
>  child_interrupt = local_state.interruptCells(0x0)
>
>  # parent unit address
>  parent_addr = 0x0
>#get this from /gem5/system/arm/dt/platforms file
>
>  for i in range(int(self.int_count)):
>  parent_interrupt = int(self.int_base) +

[gem5-users] Re: Converting KVM-taken checkpoint to atomic-needed checkpoint

[Bobby Bruce via gem5-users]

Hey Majid,

The short answer is yes, this use-case should be supported.

You can use the `--restore-with-cpu` option to restore to the Atomic CPU.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Apr 9, 2021 at 2:29 PM Majid Jalili via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> Is it practically possible to convert the KVM-taken checkpoint such that I
> can restore it with Atomic CPU? This is particularly important because I
> have to use KVM to take my checkpoints on an ARM machine and then transfer
> them to my X86 cluster to run the checkpoints.
> I cannot avoid KVM on ARM, because my simpoints are very long, and I
> cannot continue my simulation on ARM host because it is slow and not free.
>
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[gem5-users] Re: The sim_insts in stats.txt under O3 type seems to be wrong

[Bobby Bruce via gem5-users]

Hey Charlie,

I don't think there's any bug here. The debug out file is not one
instruction per line. Certain operations may be over two lines, for
example. We don't expect the number of lines in this file to equal the
number of simulated instructions so you can't compare these side-by-side.

Kind regards,
Bobby


Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Wed, Apr 7, 2021 at 7:32 PM Liyichao via gem5-users 
wrote:

> Hi all:
>
>  When I use se mode to execute an ELF under O3 type with Exec
> debug flags, the sim_insts in stats.txt is different with the lines of Exec
> debug output file.
>
>  Sim_ints is 94189557, but Exec debug output file has 472187507 lines.
> I have test the same ELF on my aarch64 server with “perf stat -e r11 -e
> r8:k -e r8:u ./redis_0327”, the r8:u is userspace instrution counts, the
> result is:
>
> 1,514,293,116 r11
> 820,116,727 r8:k
> 429,128,196 r8:u
>
> Is the count of sim_insts was wrong?It seems that the sim_insts is about a
> fifth less than the actual count of instructions.
>
>
>
>
>
> My gem5 versiont is 20.0.0.3, my command is
>
> “./build/ARM/gem5.opt --debug-flags=Exec
> --debug-file=./new_o3_debug_out.txt configs/example/se.py
> --cpu-type=DerivO3CPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches
> --l2cache --mem-size=8GB
> --nvmain-config=../../nvmain_public/Config/template_DRAM_2933.config -c
> ./redis_0327”
>
>
>
> Stats.txt:
>
> final_tick 144144768845 # Number of ticks from beginning of simulation
> (restored from checkpoints and never reset)
> host_inst_rate 18845 # Simulator instruction rate (inst/s)
> host_mem_usage 8562280 # Number of bytes of host memory used
> host_op_rate 24546 # Simulator op (including micro ops) rate (op/s)
> host_seconds 4998.02 # Real time elapsed on the host
> host_tick_rate 28840391 # Simulator tick rate (ticks/s)
> sim_freq 1 # Frequency of simulated ticks
> sim_insts 94189557 # Number of instructions simulated
> sim_ops 122680518 # Number of ops (including micro ops) simulated
> sim_seconds 0.144145 # Number of seconds simulated
> sim_ticks 144144768845 # Number of ticks simulated
>
>
>
> Exec debug output file:
>
> cat m5out/new_o3_debug_out.txt |wc -l
> 472187507
>
>
> --
>
> 李翼超（Charlie）
>
>
>
> 华为技术有限公司 Huawei Technologies Co., Ltd.
>
> [image: Company_logo]
>
> 部门：计算系统与组件开发部 [云与计算BG]
>
> 手 机：15858232899
> 电子邮件：liyic...@huawei.com
>
> 地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]
> --
>
>  本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
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[gem5-users] Re: Maybe pipeview script has some version compatibility issues？

[weiwei Zhao via gem5-users]

OK ^.^

Hoa Nguyen wrote:
> Hi,
> 
> Thanks for reporting this bug. It is indeed a python3 compatibility
> issue, which is is addressed here
> https://gem5-review.googlesource.com/c/public/gem5/+/7 and will be
> merged to the develop branch soon.
> 
> Regards,
> Hoa Nguyen
> 
> On 4/12/21, Gabe Black via gem5-users  wrote:
> > Maybe a python 2 vs 3 issue? I haven't used this script myself.
> >
> > Gabe
> >
> > On Mon, Apr 12, 2021 at 2:02 AM weiwei Zhao via gem5-users <
> > gem5-users(a)gem5.org> wrote:
> >
> >> cmd：./util/o3-pipeview.py -c 1000 -o DP1d_corr/pipeview.out --color
> >> DP1d_corr/trace.out
> >>
> >> Processing trace...  Traceback (most recent call last):
> >>   File "./util/o3-pipeview.py", line 379, in 
> >> main()
> >>   File "./util/o3-pipeview.py", line 371, in main
> >> *(tick_range + inst_range))
> >>   File "./util/o3-pipeview.py", line 142, in process_trace
> >> queue_inst(outfile, curr_inst, cycle_time, width, color, timestamps,
> >> store_completions)
> >>   File "./util/o3-pipeview.py", line 162, in queue_inst
> >> print_insts(outfile, cycle_time, width, color, timestamps,
> >> store_completions, insts['min_threshold'])
> >>   File "./util/o3-pipeview.py", line 167, in print_insts
> >> insts['queue'].sort(compare_by_sn)
> >> TypeError: must use keyword argument for key function
> >> ___
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> >
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[gem5-users] Re: About links on learing gem5

[Hoa Nguyen via gem5-users]

Hi,

Thank you for reporting this bug. The links have been updated!

Regards,
Hoa Nguyen

On 4/6/21, Ahmad SB via gem5-users  wrote:
> Hi
> Links on https://www.gem5.org/documentation/learning_gem5 are not valid
> anymore (e.g.
> gem5.org/dist/current/gem5/cpu_tests/benchmarks/bin/arm/Bubblesort )
> It would be much appreciated if the links revised correctly.
> Best Regards
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[gem5-users] Re: can't reset stats.txt when using KVM CPU

[Hoa Nguyen via gem5-users]

Hi,

final_tick and sim_insts are RootStats (they are in src/sim/root.cc)
and they won't be reset by calling reset stats.

Regards,
Hoa Nguyen

On 4/11/21, kong han via gem5-users  wrote:
> Hi all,
> Now I using the KVM CPU to run fs mode, and I try two ways to reset the
> m5out/stats.txt but all can’t work.
>
> 1)  I use the m5.stats.reset() and m5.stats.dump() functions in the
> python script before switch cpu, the m5out/stats.txt will be written. But
> then I use m5.stats.reset() and m5.stats.dump() before next times, the
> m5out/stats.txt has no changes, the final_tick, sim_insts will not be reset
> to start from 0.
>
> 2)  So I try to use the m5 –addr 0x1001
> dumpstats/resetstats/dumpresetstats after connect by m5term, but the same
> problem is still.
> I would appreciate it if someone can help me explain this problem.
>
>
>
>
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[gem5-users] Re: Question about multi-socket simulation for x86

[Jason Lowe-Power via gem5-users]

Hi Chris,

Using Garnet or SimpleNetwork with Ruby will allow you to set the latency
of each link to anything you'd like and create any topology you'd like. You
should be able to configure this to model a multi-socket system. That said,
it's unclear if any of the current protocols will model a modern
multi-socket system.

Cheers,
Jason

On Fri, Apr 9, 2021 at 10:08 AM Chris Zhang via gem5-users <
gem5-users@gem5.org> wrote:

> Dear all,
>
> I wonder is it possible to simulate a multi-socket machine for x86. I
> think there is one such option with Arm named num-cluster
> .
> Does it exist an equivalent knob in x86?
>
> Thanks!
>
> Best,
> Chris
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[gem5-users] Re: Maybe pipeview script has some version compatibility issues？

[Hoa Nguyen via gem5-users]

Hi,

Thanks for reporting this bug. It is indeed a python3 compatibility
issue, which is is addressed here
https://gem5-review.googlesource.com/c/public/gem5/+/7 and will be
merged to the develop branch soon.

Regards,
Hoa Nguyen

On 4/12/21, Gabe Black via gem5-users  wrote:
> Maybe a python 2 vs 3 issue? I haven't used this script myself.
>
> Gabe
>
> On Mon, Apr 12, 2021 at 2:02 AM weiwei Zhao via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> cmd：./util/o3-pipeview.py -c 1000 -o DP1d_corr/pipeview.out --color
>> DP1d_corr/trace.out
>>
>> Processing trace...  Traceback (most recent call last):
>>   File "./util/o3-pipeview.py", line 379, in 
>> main()
>>   File "./util/o3-pipeview.py", line 371, in main
>> *(tick_range + inst_range))
>>   File "./util/o3-pipeview.py", line 142, in process_trace
>> queue_inst(outfile, curr_inst, cycle_time, width, color, timestamps,
>> store_completions)
>>   File "./util/o3-pipeview.py", line 162, in queue_inst
>> print_insts(outfile, cycle_time, width, color, timestamps,
>> store_completions, insts['min_threshold'])
>>   File "./util/o3-pipeview.py", line 167, in print_insts
>> insts['queue'].sort(compare_by_sn)
>> TypeError: must use keyword argument for key function
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[gem5-users] Re: Maybe pipeview script has some version compatibility issues？

[Gabe Black via gem5-users]

Maybe a python 2 vs 3 issue? I haven't used this script myself.

Gabe

On Mon, Apr 12, 2021 at 2:02 AM weiwei Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> cmd：./util/o3-pipeview.py -c 1000 -o DP1d_corr/pipeview.out --color
> DP1d_corr/trace.out
>
> Processing trace...  Traceback (most recent call last):
>   File "./util/o3-pipeview.py", line 379, in 
> main()
>   File "./util/o3-pipeview.py", line 371, in main
> *(tick_range + inst_range))
>   File "./util/o3-pipeview.py", line 142, in process_trace
> queue_inst(outfile, curr_inst, cycle_time, width, color, timestamps,
> store_completions)
>   File "./util/o3-pipeview.py", line 162, in queue_inst
> print_insts(outfile, cycle_time, width, color, timestamps,
> store_completions, insts['min_threshold'])
>   File "./util/o3-pipeview.py", line 167, in print_insts
> insts['queue'].sort(compare_by_sn)
> TypeError: must use keyword argument for key function
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[gem5-users] Maybe pipeview script has some version compatibility issues？

[weiwei Zhao via gem5-users]

cmd：./util/o3-pipeview.py -c 1000 -o DP1d_corr/pipeview.out --color 
DP1d_corr/trace.out

Processing trace...  Traceback (most recent call last):
  File "./util/o3-pipeview.py", line 379, in 
main()
  File "./util/o3-pipeview.py", line 371, in main
*(tick_range + inst_range))
  File "./util/o3-pipeview.py", line 142, in process_trace
queue_inst(outfile, curr_inst, cycle_time, width, color, timestamps, 
store_completions)
  File "./util/o3-pipeview.py", line 162, in queue_inst
print_insts(outfile, cycle_time, width, color, timestamps, 
store_completions, insts['min_threshold'])
  File "./util/o3-pipeview.py", line 167, in print_insts
insts['queue'].sort(compare_by_sn)
TypeError: must use keyword argument for key function
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