[gem5-users] Re: A puzzle about how TLB is emulated

[Leon Zhao via gem5-users]

Hi Jason & Nathanael,

Thank you for both of your informative replies. These have been really helpful.

Leon
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[gem5-users] Re: A puzzle about how TLB is emulated

[Leon Zhao via gem5-users]

Hi Jason,

Thank you for such elaborate explanation. I will look into it.

Another weird thing happened today. I noticed that while running a benchmark, 
TLB seemed to have never triggered a miss condition. I came to this conclusion 
because TLB always started and ended at the same tick according to my console 
(my printfs' doing), even for the first few entries since real simulation.

Does this seem natural to you? Should I, in your view, run the benchmark much 
longer and then, like, redirect the output into a file to analyze the tick 
difference? Or maybe I misoperated something?

Looking forward to your reply!
Leon
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[gem5-users] TimingCPU's IPC

[Liyichao via gem5-users]

Hi All:
 As I know, Atomic or Timing CPU’s IPC is 1 IPC, but when I test a 
program in SE mode with –debug-flags=Exec, in the debug output file, I find 
that one instruction’s tick is incremented by 1000, my cpu frequency is 2 GHz. 
Does that mean that the IPC is 0.5(cycle=1000/500)?
Is the 1IPC is calculated under 1GHz?


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[gem5-users] Re: A puzzle about how TLB is emulated

[Nathanael Premillieu via gem5-users]

Hello,

Although not modelled, they do have an impact on performance for the O3 model.
Upon a TLB miss, the access is considered as faulty, triggering a pipeline 
flush and a re-execution.
At that point, the SE page table has been populated and the access gets its 
translation.

Also, I assume that the TLB hit latency is not modelled as it happens in 
parallel to the L1 cache access. But this assumption only hold if your cache 
access latency Is higher than the TLB hit latency (which is usually the case).

Thanks,
Nathanael

From: Jason Lowe-Power via gem5-users [mailto:gem5-users@gem5.org]
Sent: Thursday, April 22, 2021 10:12 PM
To: gem5 users mailing list 
Cc: Θοδωρής Τροχάτος ; Jason Lowe-Power 

Subject: [gem5-users] Re: A puzzle about how TLB is emulated

Hello,

As far as I know, TLB misses are not modeled in SE mode at all.

Cheers,
Jason

On Thu, Apr 22, 2021 at 12:50 PM Θοδωρής Τροχάτος via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi Jason! Thanks for the info!

Do you know what is happening when there is a TLB miss in SE mode?
Is the latency of a TLB miss modeled in some way in SE?
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