[gem5-users] How are system calls handled in FS mode?

2021-06-22 Thread Balls Mahoney via gem5-users
I am confused about how system calls work in Full System mode (x86). For example, in src/arch/x86/isa/decoder/two_byte_opcodes.isa for FS mode only sysenter() is called (included code below). However, I don't see this function defined anywhere else. Is this something passed straight to the kernel?

[gem5-users] Re: Regarding Cache Clusivity

2021-06-22 Thread Chongzhi Zhao via gem5-users
Hi gem5 community, Any suggestions on this topic? On Thu, May 27, 2021 at 11:29 AM Chongzhi Zhao wrote: > Update: > To enforce strict inclusivity, I changed BaseCache::handleEvictions() to > below (changes in bold font). I also added "fully_incl" to Enum in > Cache.py. > Would this make caches

[gem5-users] Re: Understanding write timing in MemCtrl

2021-06-22 Thread Jason Lowe-Power via gem5-users
Hi Vincent, It depends on when/how you're ending the simulation. If you end the simulation at some particular tick, then you'll see writes left in the write queue. Just like a real machine, writes don't happen instantaneously, and at some point in time, there are writes sitting in the write

[gem5-users] Re: Understanding write timing in MemCtrl

2021-06-22 Thread Vincent R. via gem5-users
Hi again, just wanted to give this a second try. No urgent matter here, just some lack of understanding and curiosity on my side. Thank you, Vincent Am 04.06.2021 um 11:34 schrieb Vincent R.: Hi everyone, I am currently doing some experiments with packet timings in the Memory Controller(

[gem5-users] Re: Read request and writebacks in gem5

2021-06-22 Thread Aritra Bagchi via gem5-users
Any help from anyone is appreciated. Thanks! Regards, Aritra On Tue, Jun 22, 2021, 01:18 Aritra Bagchi wrote: > Hi, > > Could anybody help me understand what happens in gem5 when a read request > reaches a cache (say L3) and L2's write queue has a pending writeback > (writeback that has not

[gem5-users] HMC in SE mode using a single vault controller

2021-06-22 Thread hissa alshamsi via gem5-users
Hi everyone, I am trying to use HMC in SE mode. The problem is when I run hello world binary file or any other larger benchmark, apparently from stats.txt only one vault controller is being used. I don't know why the other controllers are shown to be in IDLE state with zero values. I have