[gem5-users] Simulation memory Object with Atomic Requests and Responses

[Abdlerhman Abotaleb]

Hello All, 
I'm trying to implement a simulation memory object that accepts atomic requests on its CPUSide port (response port) and forwards them to the memory controller.


This simulation object is connected to cache from the CPUSidePort and to Memory controller from memSidePort.

It works fine with timing requests and responses. 

For Atomic requests, I override the recvAtomic making it calls sendAtomic in the Request port
         Inside the CPUSidePort(which is defined inside the simulation object scope , inherit from ResponsePort) :
         Tick recvAtomic(PacketPtr pkt) override
          {            
              owner->handleAtomic(pkt);           // handleAtomic  defined in the simulation object

          }

        &  Inside the Simulation object:


     void
         simulationMemObect::handleAtomic(PacketPtr pkt)
 {

 memSidePort.sendAtomic(pkt); 
    }


I don't know how to implement the response receive handling , there's no function to override called recAtomicResp , similar to recvTimingResp in TimingRequestProtocol (One of RequestPort class parents).


For now, If run GEM5 , it ends with core dump at the beginning with the following output when try to debug with GDB:


received signal SIGILL, Illegal instruction.

0x0117bdf1
in



gem5:: simulationMemObect ::CPUSidePort::recvAtomic(gem5::Packet*)




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[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

[Jason Lowe-Power]

Hi Zehan,

I wouldn't say it converts the timing request to atomic. Instead, I would
say that for the *functional access* (sorry for the overloaded term here...
I mean functional as in the place it does the "execution" part of the
model) it uses the same C++ function for both timing and atomic. The timing
should be handled in the delay when the sendTimingReq or sendTimingResp
events are scheduled.

Cheers,
Jason

On Wed, Jul 6, 2022 at 8:21 AM Zehan Gao  wrote:

> Thanks for your advice. My guess is that it's the ports connected to the
> atomic-only port converts a timing request to atomic, and calls the
> recvAtomic function. In this case it's the XBar. I will try to measure how
> it's delayed.
>
> --
> *From:* Jason Lowe-Power 
> *Sent:* Wednesday, July 6, 2022, 11:09 a.m.
> *To:* The gem5 Users mailing list 
> *Subject:* [gem5-users] Re: What happens when a atomic only port is
> accessed in Timing simulation?
>
> Hi Zehan,
>
> Atomic memory accesses should not be used during the same simulation loop
> as timing accesses. I.e., you should not call "sendAtomic" on a port during
> the same simulation loop that you call "sendTiming". If there isn't a panic
> in that case, there probably should be.
>
> If you want to get a value out of memory in 0 time (e.g., for debugging or
> to model a "perfect" hardware component) you can use *functional* accesses
> during the timing simulation. You can also exit the simulation loop and
> switch between timing and atomic modes.
>
> Cheers,
> Jason
>
> On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao  wrote:
>
>> Hi All,
>>
>>   I am building a simulated system with a control registers
>> port that only implemented recvAtomic function. The control port is
>> connected to the IOBridge, and the system is running in timing mode. There
>> is no problem to access the registers from CPU, but I wonder what the
>> system does with the delay? I believe the atomic port would be treated as a
>> timing port that has no delays. But is the delay of IOBridge and other
>> system buses counted?
>>
>>
>>
>> Thanks,
>>
>> Zehan
>>
>>
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>
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[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

[Zehan Gao]

Thanks for your advice. My guess is that it's the ports connected to the 
atomic-only port converts a timing request to atomic, and calls the recvAtomic 
function. In this case it's the XBar. I will try to measure how it's delayed.


From: Jason Lowe-Power 
Sent: Wednesday, July 6, 2022, 11:09 a.m.
To: The gem5 Users mailing list 
Subject: [gem5-users] Re: What happens when a atomic only port is accessed in 
Timing simulation?

Hi Zehan,

Atomic memory accesses should not be used during the same simulation loop as 
timing accesses. I.e., you should not call "sendAtomic" on a port during the 
same simulation loop that you call "sendTiming". If there isn't a panic in that 
case, there probably should be.

If you want to get a value out of memory in 0 time (e.g., for debugging or to 
model a "perfect" hardware component) you can use *functional* accesses during 
the timing simulation. You can also exit the simulation loop and switch between 
timing and atomic modes.

Cheers,
Jason

On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao 
mailto:z99...@uwaterloo.ca>> wrote:
Hi All,
  I am building a simulated system with a control registers port 
that only implemented recvAtomic function. The control port is connected to the 
IOBridge, and the system is running in timing mode. There is no problem to 
access the registers from CPU, but I wonder what the system does with the 
delay? I believe the atomic port would be treated as a timing port that has no 
delays. But is the delay of IOBridge and other system buses counted?

Thanks,
Zehan

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[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

[Jason Lowe-Power]

Hi Zehan,

Atomic memory accesses should not be used during the same simulation loop
as timing accesses. I.e., you should not call "sendAtomic" on a port during
the same simulation loop that you call "sendTiming". If there isn't a panic
in that case, there probably should be.

If you want to get a value out of memory in 0 time (e.g., for debugging or
to model a "perfect" hardware component) you can use *functional* accesses
during the timing simulation. You can also exit the simulation loop and
switch between timing and atomic modes.

Cheers,
Jason

On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao  wrote:

> Hi All,
>
>   I am building a simulated system with a control registers
> port that only implemented recvAtomic function. The control port is
> connected to the IOBridge, and the system is running in timing mode. There
> is no problem to access the registers from CPU, but I wonder what the
> system does with the delay? I believe the atomic port would be treated as a
> timing port that has no delays. But is the delay of IOBridge and other
> system buses counted?
>
>
>
> Thanks,
>
> Zehan
>
>
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>
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[gem5-users] Re: Difference between configs/ruby scripts vs. learning_gem5/part3 config scripts

[gabriel . busnot]

Hi Gautam,

When configuring more complex systems, the python run-script tends to spread 
over several to many .py files. In case of Ruby, each protocol PROT has a main 
configuration file: configs/ruby/PROT.py. (It can then use other files like CHI 
that has CHI.py as its configuration entry point and CHI_config.py imported by 
CHI.py). 

The main entry point to these scripts is configs/ruby/Ruby.py, specifically the 
create_system function. The bloc starting with `protocol = buildEnv['PROTOCOL'] 
`is where the magic happens to import the correct PROT.py file.

Then, from your top configuration file:

> `from ruby import Ruby`
>
> `Ruby.create_system(…)`

Et voilà! You have plenty of examples in configs/example/ruby_XXX_test.py

Best,

Gabriel
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[gem5-users] Re: Can I use another c++ compiler to build gem5 ?

[gabriel . busnot]

Hi,

Here is a patch from my personal modifications to SConstruct. It makes scons 
use the system-wide cc/c++ aliases that you can rebind to your liking with, 
e.g., update-alternatives on ubuntu. I’ve tested it successfully with several 
flavors of gcc/clang together with the ld or lld linker (the later being 
noticeably faster on my system). In any case, you can adapt the patch to 
hardcode your compiler in it. Beware with the compiler version checking that is 
a bit picky ;)

Gabriel
diff --git a/SConstruct b/SConstruct
index 4d91eae3f0..d5bb324b1e 100755
--- a/SConstruct
+++ b/SConstruct
@@ -179,8 +179,11 @@ main = Environment(tools=[
 ConfigFile, AddLocalRPATH, SwitchingHeaders, TagImpliesTool, Blob
 ])
 
-main.Tool(SCons.Tool.FindTool(['gcc', 'clang'], main))
-main.Tool(SCons.Tool.FindTool(['g++', 'clang++'], main))
+main.Tool(SCons.Tool.FindTool(['cc', 'gcc', 'clang'], main))
+main.Tool(SCons.Tool.FindTool(['c++', 'g++', 'clang++'], main))
+
+main['CC'] = 'cc'
+main['CXX'] = 'c++'
 
 Export('main')
 
@@ -285,7 +288,8 @@ main['TCMALLOC_CCFLAGS'] = []
 
 CXX_version = readCommand([main['CXX'], '--version'], exception=False)
 
-main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
+main['GCC'] = CXX_version and \
+(CXX_version.find('g++') >= 0 or CXX_version.find('c++') >= 0)
 main['CLANG'] = CXX_version and CXX_version.find('clang') >= 0
 if main['GCC'] + main['CLANG'] > 1:
 error('Two compilers enabled at once?')
@@ -418,13 +422,6 @@ for variant_path in variant_paths:
 conf.CheckLinkFlag(
 '-Wl,--thread-count=%d' % GetOption('num_jobs'))
 
-# Treat warnings as errors but white list some warnings that we
-# want to allow (e.g., deprecation warnings).
-env.Append(CCFLAGS=['-Werror',
- '-Wno-error=deprecated-declarations',
- '-Wno-error=deprecated',
-])
-
 else:
 error('\n'.join((
   "Don't know what compiler options to use for your compiler.",
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