[gem5-users] Creating custom stat in gem5 and dumping them to stats file.
Hi All, I am using gem5 v19. My requirement is to track the number of accesses made by a core to a cache block. I will need to keep a map with the key as the cache block address and the value as the total number of accesses to the block. Is it possible to add new custom stats (based on unordered map in this scenario) to Gem5 and then dump the custom stats to the stat file at the end of the simulation? Regards, Vipin ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Add custom Register In ARM
Hi, If you are just planning on introducing a single register, you could consider extending the number of IntRegs, or to add this extra register as a MiscReg (but be careful in the latter case, as MiscRegs are not renamed). If you really want to define a new register class, we have recently pushed some patches which are implementing FEAT_SME in gem5 by adding matrix registers. I suggest you have a look at the following patches: https://gem5-review.googlesource.com/c/public/gem5/+/64333/1 https://gem5-review.googlesource.com/c/public/gem5/+/64334/1 You could use them as an example/to get an idea on what should be done Kind Regards Giacomo From: 等价无穷小 via gem5-users Date: Tuesday, 29 November 2022 at 11:15 To: gem5-users Cc: 等价无穷小 Subject: [gem5-users] Add custom Register In ARM Hi all, Recently, I wanted to add a new custom register in gem5, and the load/store instruction can take the custom register as src/dest register to move data from memory. Is there some suggestions about this? And I have some confusion about the register implementation in gem5. In src/cpu/reg_class.hh/cc file, defining the RegClass and RegId class, if I add a new custom register, should I add a new Regclass, like CustomClass, and give it new RegId? And in the src/arch/arm, there are five files about the register: ccregs.hh、intregs.hh、miscregs.hh/cc 、registers.hh .In these files, everyone of these file almost enumorate the RegIndex, I understand it just a signature of a register, how can i map the register to the signature? Thanks, ZhangMeng IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Add custom Register In ARM
Hi all, Recently, I wanted to add a new custom register in gem5, and the load/store instruction can take the custom register as src/dest register to move data from memory. Is there some suggestions about this? And I have some confusion about the register implementation in gem5. In src/cpu/reg_class.hh/cc file, defining the RegClass and RegId class, if I add a new custom register, should I add a new Regclass, like CustomClass, and give it new RegId? And in the src/arch/arm, there are five files about the register: ccregs.hh??intregs.hh??miscregs.hh/cc ??registers.hh .In these files, everyone of these file almost enumorate the RegIndex, I understand it just a signature of a register, how can i map the register to the signature? Thanks, ZhangMeng___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Simulation of ARM TrustZone
Hello, yes, it is supported. You could use the following blog post [1] as a starting point. There was also a talk at the ISCA2022 workshop about booting OP-TEE in gem5; you could probably look for it on youtube IIRC Kind Regards Giacomo [1]: https://community.arm.com/arm-research/b/articles/posts/running-trusted-firmware-a-on-gem5 From: Pavitra bhade via gem5-users Date: Tuesday, 29 November 2022 at 07:33 To: gem5-users@gem5.org , gem5-users-confirm+e2f5a27c00581d0f4a3594969c833c80e0f57...@gem5.org , gem5-users-j...@gem5.org Cc: Pavitra bhade Subject: [gem5-users] Simulation of ARM TrustZone Dear All, I am interested in simulating the ARM TrustZone on Gem5. Is that supported? -- Pavitra Prakash Bhade Ph.D. Student Indian Institute of Technology Goa ** This e-mail is for the sole use of the intended recipient(s) and may contain confidential and privileged information. If you are not the intended recipient, please contact the sender by reply e-mail and destroy all copies and the original message. Any unauthorized review, use, disclosure, dissemination, forwarding, printing or copying of this email is strictly prohibited and appropriate legal action will be taken. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
