[gem5-users] MSI Protocol at Memory
Hello everyone I’m an undergraduate student and going to embark on a journey to extend the protocol for MESI_Three_Level at the memory level to MSI or MESI, as opposed to the two-state MI that it is right now. Does anyone have any tips or advice for this journey, perhaps one of you has done something similar or already have this implemented? I understand that at a minimum, this requires modifying both the memory SLICC protocol and also the last level cache. Thanks a lot, Arteen UCLA ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Is SMT Supported in ARM Full System Simulation
Hi all, You can in principle try to setup an SMT simulation for the O3CPU by tweaking the smt parameters of the CPU [1] In practice this has not been tested in a long time and it is very likely it is broken. Kind Regards Giacomo [1]: https://github.com/gem5/gem5/blob/stable/src/cpu/o3/BaseO3CPU.py#L177 From: Eliot Moss via gem5-users Date: Tuesday, 10 October 2023 at 13:29 To: The gem5 Users mailing list Cc: Abdelrahman S. Hussein , Eliot Moss Subject: [gem5-users] Re: Is SMT Supported in ARM Full System Simulation On 10/10/2023 4:04 AM, Abdelrahman S. Hussein via gem5-users wrote: > Hello, > > I am considering using ARM ISA for simulation on gem5. I understand that SMT > is NOT supported for Full System Simulation > for x86. I just would like to know if gem5 supports SMT for Full System > simulation in ARM ISA. Not as far as I know. This has to do with the underlying generic models used in gem5. They are customized to each instruction set by fiddling parameters, adding functional units, etc., and of course the instruction formats and actions can be adjusted. But the nature of the models (in-order, out-of-order) are the same. If I am wrong I'm sure someone will correct me! Best wishes - Eliot Moss ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Is SMT Supported in ARM Full System Simulation
On 10/10/2023 4:04 AM, Abdelrahman S. Hussein via gem5-users wrote: Hello, I am considering using ARM ISA for simulation on gem5. I understand that SMT is NOT supported for Full System Simulation for x86. I just would like to know if gem5 supports SMT for Full System simulation in ARM ISA. Not as far as I know. This has to do with the underlying generic models used in gem5. They are customized to each instruction set by fiddling parameters, adding functional units, etc., and of course the instruction formats and actions can be adjusted. But the nature of the models (in-order, out-of-order) are the same. If I am wrong I'm sure someone will correct me! Best wishes - Eliot Moss ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Is SMT Supported in ARM Full System Simulation
Hello, I am considering using ARM ISA for simulation on gem5. I understand that SMT is NOT supported for Full System Simulation for x86. I just would like to know if gem5 supports SMT for Full System simulation in ARM ISA. Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
