Regarding the following cache memory latency parameters:
Tag latency
Data latencyResponse latency
The default values for "L2 Cache" are 20 cycles per each.
Are those values seem to be practical?
What is the total latency for an access that hits in L2 Cache?
(L1 Miss + L2 Hit)
Should
I want to do a fast forwarding.
i.e. run most of the source with AtomicSimpleCPU till encounter "m5_switch_cpu" then use Minor CPU.
I used the following options when running GEM5 binary:
"--cpu-type MinorCPU --fast-forward=100"
I got a segmentation fault, and when
How to use different physical addresses for two programs run on
two processors?
I can find that using "malloc" allocates the same addresses
Also, I'm using the same binary on the two processors.
Thanks.
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SCONS Produce debug symbols for GEM5 except for shared libraries.
i.e. If I integrate any module in ext folder with GEM5 it is compiled
and linked as a shared library without debug symbols being added.
What is the modification should I make to sconstruct or SConscript
to enable shared
I have a program bin.riscv that is running on 4 prcoessors simulatenously.
Inside riscv.bin:
// some code
m5_checkpoint(0,0);
m5_reset_stats(0,0);
// some code
I'm running GEM5 using the following commands:
First
gem5.opt ./configs/example/se.py -n 4 --caches
I want to identify the source CPU# of a packet.
I found a field called "pkt->requestorId()"
This field originally can have the following options: "Source: gem5/src/mem/request.hh"
wbRequestorId = 0, /* writeback requests by the caches */
funcRequestorId = 1, /* functional
How to enforce the TLB in the system emulated (SE) mode to always produce
Page Frame Number = Virtual Page Number.
I may want to try two things:
Don't disable the TLB but have PFN=VPNDisable TLB , so addresses in the workload are physical addresses.
Thanks, a lot.
An interesting thing that I found when analyzing GEM5 output, is that core 7 hits the reset stats after core 0 finishes, this happens in very special scenario if scheduling favorites a core over another, so now this makes sense.
From: Abdlerhman Abotaleb via gem5-users
Sent: Saturday
How can I share a variable between multicores in GEM5. (I'm simulating RISCV- Cores)
I can see that each core allocates different VPN to PFN translation.
So even if I explicitly assign a memory address to a variable (i.e. char*arr = 0x20010 then dereference it later) it will be in different
How reset stats work in case of multicore ?
I run multicore experiment with 8 cores running the same binary.
The binary has m5_reset_stats(0,0); before code of interest which is a loop that runs huge number of iterations (for example 100k ~ access 781kB of data ,in case of double type
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