[gem5-users] m5threads compile error

2019-04-02 Thread 조해윤
Dear. all

I'm trying to compile m5threads.

At the m5threads directory, when I run the command
gcc -static -c pthread.c -o pthread.o

the error occurs like below.

pthread.c: In function ‘pthread_create’:
pthread.c:256:3: warning: implicit declaration of function ‘clone’; did you
mean ‘close’? [-Wimplicit-function-declaration]
   clone(__pthread_trampoline, tcb->stack_start_addr,
CLONE_VM|CLONE_FS|CLONE_FILES|CLONE_SIGHAND|CLONE_THREAD, tcb);
   ^
   close
In file included from pthread.c:49:0:
pthread.c: In function ‘pthread_rwlock_init’:
pthread_defs.h:102:73: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__lock’
 efine PTHREAD_RWLOCK_T_LOCK(rwlock)  (*(volatile
int*)(>__data.__lock))
   ^
pthread.c:380:5: note: in expansion of macro ‘PTHREAD_RWLOCK_T_LOCK’
 PTHREAD_RWLOCK_T_LOCK(lock) = 0; // used only with spin_lock, so we
know to initilize to zero
 ^
pthread_defs.h:103:77: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__nr_readers’; did you mean ‘__readers’?
 PTHREAD_RWLOCK_T_READERS(rwlock)  (*(volatile
int*)(>__data.__nr_readers))
 ^
pthread.c:381:5: note: in expansion of macro ‘PTHREAD_RWLOCK_T_READERS’
 PTHREAD_RWLOCK_T_READERS(lock) = 0;
 ^~~~
pthread_defs.h:104:76: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__writer’; did you mean ‘__writers’?
 e PTHREAD_RWLOCK_T_WRITER(rwlock)  (*(volatile
int*)(>__data.__writer))
  ^
pthread.c:382:5: note: in expansion of macro ‘PTHREAD_RWLOCK_T_WRITER’
 PTHREAD_RWLOCK_T_WRITER(lock) = -1; // -1 means no one owns the write
lock
 ^~~
pthread.c: In function ‘pthread_rwlock_rdlock’:
pthread_defs.h:104:76: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__writer’; did you mean ‘__writers’?
 e PTHREAD_RWLOCK_T_WRITER(rwlock)  (*(volatile
int*)(>__data.__writer))
  ^
pthread.c:398:32: note: in expansion of macro ‘PTHREAD_RWLOCK_T_WRITER’
 pthread_t writer = PTHREAD_RWLOCK_T_WRITER(lock);
^~~
pthread_defs.h:102:73: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__lock’
 efine PTHREAD_RWLOCK_T_LOCK(rwlock)  (*(volatile
int*)(>__data.__lock))
   ^
pthread.c:404:27: note: in expansion of macro ‘PTHREAD_RWLOCK_T_LOCK’
 spin_lock((int*)&(PTHREAD_RWLOCK_T_LOCK(lock)));
   ^
pthread_defs.h:104:76: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__writer’; did you mean ‘__writers’?
 e PTHREAD_RWLOCK_T_WRITER(rwlock)  (*(volatile
int*)(>__data.__writer))
  ^
pthread.c:405:24: note: in expansion of macro ‘PTHREAD_RWLOCK_T_WRITER’
 if ((pthread_t)PTHREAD_RWLOCK_T_WRITER(lock) == -1) {
^~~
pthread_defs.h:103:77: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__nr_readers’; did you mean ‘__readers’?
 PTHREAD_RWLOCK_T_READERS(rwlock)  (*(volatile
int*)(>__data.__nr_readers))
 ^
pthread.c:406:13: note: in expansion of macro ‘PTHREAD_RWLOCK_T_READERS’
 PTHREAD_RWLOCK_T_READERS(lock)++;
 ^~~~
pthread_defs.h:102:73: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__lock’
 efine PTHREAD_RWLOCK_T_LOCK(rwlock)  (*(volatile
int*)(>__data.__lock))
   ^
pthread.c:407:33: note: in expansion of macro ‘PTHREAD_RWLOCK_T_LOCK’
 spin_unlock((int*)&(PTHREAD_RWLOCK_T_LOCK(lock)));
 ^
pthread_defs.h:102:73: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__lock’
 efine PTHREAD_RWLOCK_T_LOCK(rwlock)  (*(volatile
int*)(>__data.__lock))
   ^
pthread.c:411:29: note: in expansion of macro ‘PTHREAD_RWLOCK_T_LOCK’
 spin_unlock((int*)&(PTHREAD_RWLOCK_T_LOCK(lock)));
 ^
pthread.c: In function ‘pthread_rwlock_wrlock’:
pthread_defs.h:104:76: error: ‘struct __pthread_rwlock_arch_t’ has no
member named ‘__writer’; did you mean ‘__writers’?
 e PTHREAD_RWLOCK_T_WRITER(rwlock)  (*(volatile
int*)(>__data.__writer))
  ^
pthread.c:422:32: note: in expansion of macro ‘PTHREAD_RWLOCK_T_WRITER’
 pthread_t writer = PTHREAD_RWLOCK_T_WRITER(lock);
^~~

[gem5-users] How can I run the Ligra framework in gem5 x86 SE mode?

2019-02-10 Thread 조해윤
Dear. all.

As a graph analysis benchmark suite, I'm considering the Lirga framework
which is multi-thread program using the OpenMP.

I found the paper (A. Addisie, et al., "Heterogeneous Memory Subsystem for
Natural Graph Analytics," IISWC, 2018) which run Ligra on x86 SE mode, so
running Ligra on x86 SE mode seems possible.

To complie the Ligra framework, I referenced the slides (
http://www.csl.cornell.edu/~cbatten/pdfs/ta-gem5-riscv-slides-carrv2018.pdf)
which run the Ligra on RISC-V SE mode.

Before compiling, I modified some codes of ligra.h.
sed '/long rounds/a int num cpu = P.getOptionIntValue("-n",1);
setWorkers(num cpu);' ligra.h.old > ligra.h
This modification looks for supporting the option "-n" indicating the numer
of threads.

At a first try, I compiled like below.
gcc -static -std=c++14 -fopenmp -DOPENMP -Wall -O0 -I. -c BFS.C -o BFS.o
g++ -static -std=c++14 -DOPENMP -L. -o BFS BFS.o -lgomp -lpthread -ldl

The gem5 command was like below.
./build/X86/gem5.opt configs/example/se.py --cpu-type=DerivO3CPU -n 4
--caches --ruby --network=garnet2.0 --num-dirs=4 -c
/home/haeyoon/ligra/apps/BFS -o "-n 4
/home/haeyoon/ligra/inputs/rMatGraph_J_5_100"

The first error that I met was like below.
fatal: syscall getdents (#78) unimplemented.

To avoid this error, I made syscall getdents as ignoreFunction.

Then, I met second error like below.
Running time : 0.000323
Running time : 0.000327
Running time : 0.000334
fatal: Ruby functional read failed for address 0x222e44

Something more weired is that if I run without ruby system, in other words
classic memory system, I even can't see the BFS output also.
Exiting @ tick 18446744073709551615 because simulate() limit reached

After this, I found that pthread is not possible in SE mode so that
m5threads is needed.
So, I compiled like below.
g++ -static -std=c++14 -DOPENMP -L. -o BFS BFS.o -lgomp
/home/haeyoon/m5threads/libpthread.a -ldl
However, the error is still same.

In this point, I have additional question. Is the pthread is possible in
gem5 SE mode now??
If not, why the error is same? Or my compile process is wrong?

Is there anyone who can give me some advice to run the Ligra framework in
gem5 SE mode?

Best Regards.
Haeyoon Cho.
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Re: [gem5-users] The simulator can't read the contents of the rcS file

2018-06-08 Thread 조해윤
Dear Jung Min You.

The full system mode includes the operating system and the script which be
entered with --script option is the script file which be run after OS is
booted.
In case of SE mode, the result of a benchmark is printed in the terminal
which you write command line.
In case of FS mode, the result of a benchmark is printed in OS terminal (I
don't know this express is correct, but there is another terminal).
Related with telnet, see the full system mode section of follow link,
http://gem5.org/Running_gem5.
In contrast to SE mode, FS mode makes additional outputs like
system.terminal.

Let's see a file, system.terminal, which is the output of OS.

Best regards,

Haeyoon Cho.

2018-06-08 16:59 GMT+09:00 류정민 :

> Dear Haeyoon Cho,
>
> I mean the terminal which I type command line.
>
> I know that the echo command writes statement on the terminal which I type
> command lines.
>
> By the way, what do you mean boot?
>
> Do I need to boot gem5 to use script file?
>
> Best regards,
>
> Jung Min You
>
> 2018-06-08 16:43 GMT+09:00 조해윤 :
>
>> Dear Jung Min You.
>>
>> It is strange. Is it booted well?
>>
>> What the terminal you mean?
>> Is it terminal of telnet? Or is it terminal which you typed command line?
>>
>> The file, system.terminal, is the same result of the telnet terminal.
>>
>> Best regards,
>>
>> Haeyoon Cho.
>>
>> 2018-06-08 16:18 GMT+09:00 류정민 :
>>
>>> Dear Haeyoon Cho,
>>>
>>> I changed script file and run the simulation again.
>>>
>>> the script file as follows
>>>
>>>
>>>
>>> # !/bin/sh
>>> echo "let's start benchmark simulation"
>>>
>>> cd /parsec/parsec/install/bin
>>>
>>> /parsec/sbin/m5 dumpstats
>>> /parsec/sbin/m5 resetstats
>>>
>>> ./blackscholes 64 /parsec/parsec/install/inputs/blackscholes/in_16K.txt
>>> /parsec/parsec/install/inputs/blackscholes/prices.txt
>>>
>>> echo "finish! :D"
>>>
>>> /parsec/sbin/m5 exit
>>> /parsec/sbin/m5 exit
>>>
>>>
>>>
>>>
>>> Same as the previous case, the echo statements didn't print on the
>>> terminal.
>>>
>>> As the echo statement located at the first line, I think it must be
>>> printed.
>>>
>>> Thanks.
>>>
>>> Best regards,
>>>
>>> Jung Min.
>>>
>>>
>>> 2018-06-08 15:50 GMT+09:00 조해윤 :
>>>
>>>> Dear Jung Min You.
>>>>
>>>> The command line looks fine.
>>>>
>>>> How did you write the script?
>>>> The hack_back_ckpt.rcS is basically for checkpoint.
>>>> This script detect itself whether is was run before, in other words,
>>>> the simulation was restored by the checkpoint.
>>>> Thus, depend on the position of the echo command in your script, it may
>>>> not run.
>>>>
>>>> Best regards,
>>>>
>>>> Haeyoon Cho.
>>>>
>>>> 2018-06-08 11:41 GMT+09:00 류정민 :
>>>>
>>>>> Hi,
>>>>>
>>>>> my name is Jung Min You and I'm graduated course student in
>>>>> Sungkyunkwan University, South Korea.
>>>>>
>>>>> I followed your tutorial to study about gem5.
>>>>>
>>>>> For my research, I need to simulate the system using a gem5 full
>>>>> system mode.
>>>>>
>>>>> When I tried to run the fs mode, I used the script files located in
>>>>> gem5/configs/boot/~~.rcS.
>>>>>
>>>>> Meanwhile, to debug the result, I inserted some echo statement in the
>>>>> script file.
>>>>>
>>>>> However, no debug statement has printed in terminal.
>>>>>
>>>>> I tried to use hack_back_ckpt.rcS, and my command line as follows.
>>>>>
>>>>> build/X86/gem5.opt configs/example/fs.py --cpu-type="AtomicSimpleCPU"
>>>>> --caches --l1i_size=32kB --l1d_size=32kB --l2_size=2MB -F 2 -I
>>>>> 2 --kernel=$GEM5_DIR/system/binaries/x86_64-vmlinux-2.6.22.9.smp
>>>>> --disk-image=$GEM5_DIR/system/disks/linux-x86.img
>>>>> --script=configs/boot/hack_back_ckpt.rcS
>>>>>
>>>>> If there is any mistakes in my simulation progress, please tell me
>>>>> what is the problem.
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Jung Min.
>>>>>
>>>>>
>>>>> ___
>>>>> gem5-users mailing list
>>>>> gem5-users@gem5.org
>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>>
>>>>
>>>>
>>>> ___
>>>> gem5-users mailing list
>>>> gem5-users@gem5.org
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>
>>>
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Re: [gem5-users] The simulator can't read the contents of the rcS file

2018-06-08 Thread 조해윤
Dear Jung Min You.

It is strange. Is it booted well?

What the terminal you mean?
Is it terminal of telnet? Or is it terminal which you typed command line?

The file, system.terminal, is the same result of the telnet terminal.

Best regards,

Haeyoon Cho.

2018-06-08 16:18 GMT+09:00 류정민 :

> Dear Haeyoon Cho,
>
> I changed script file and run the simulation again.
>
> the script file as follows
>
>
>
> # !/bin/sh
> echo "let's start benchmark simulation"
>
> cd /parsec/parsec/install/bin
>
> /parsec/sbin/m5 dumpstats
> /parsec/sbin/m5 resetstats
>
> ./blackscholes 64 /parsec/parsec/install/inputs/blackscholes/in_16K.txt
> /parsec/parsec/install/inputs/blackscholes/prices.txt
>
> echo "finish! :D"
>
> /parsec/sbin/m5 exit
> /parsec/sbin/m5 exit
>
>
>
>
> Same as the previous case, the echo statements didn't print on the
> terminal.
>
> As the echo statement located at the first line, I think it must be
> printed.
>
> Thanks.
>
> Best regards,
>
> Jung Min.
>
>
> 2018-06-08 15:50 GMT+09:00 조해윤 :
>
>> Dear Jung Min You.
>>
>> The command line looks fine.
>>
>> How did you write the script?
>> The hack_back_ckpt.rcS is basically for checkpoint.
>> This script detect itself whether is was run before, in other words, the
>> simulation was restored by the checkpoint.
>> Thus, depend on the position of the echo command in your script, it may
>> not run.
>>
>> Best regards,
>>
>> Haeyoon Cho.
>>
>> 2018-06-08 11:41 GMT+09:00 류정민 :
>>
>>> Hi,
>>>
>>> my name is Jung Min You and I'm graduated course student in Sungkyunkwan
>>> University, South Korea.
>>>
>>> I followed your tutorial to study about gem5.
>>>
>>> For my research, I need to simulate the system using a gem5 full system
>>> mode.
>>>
>>> When I tried to run the fs mode, I used the script files located in
>>> gem5/configs/boot/~~.rcS.
>>>
>>> Meanwhile, to debug the result, I inserted some echo statement in the
>>> script file.
>>>
>>> However, no debug statement has printed in terminal.
>>>
>>> I tried to use hack_back_ckpt.rcS, and my command line as follows.
>>>
>>> build/X86/gem5.opt configs/example/fs.py --cpu-type="AtomicSimpleCPU"
>>> --caches --l1i_size=32kB --l1d_size=32kB --l2_size=2MB -F 2 -I
>>> 2 --kernel=$GEM5_DIR/system/binaries/x86_64-vmlinux-2.6.22.9.smp
>>> --disk-image=$GEM5_DIR/system/disks/linux-x86.img
>>> --script=configs/boot/hack_back_ckpt.rcS
>>>
>>> If there is any mistakes in my simulation progress, please tell me what
>>> is the problem.
>>>
>>> Best regards,
>>>
>>> Jung Min.
>>>
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Re: [gem5-users] The simulator can't read the contents of the rcS file

2018-06-08 Thread 조해윤
Dear Jung Min You.

The command line looks fine.

How did you write the script?
The hack_back_ckpt.rcS is basically for checkpoint.
This script detect itself whether is was run before, in other words, the
simulation was restored by the checkpoint.
Thus, depend on the position of the echo command in your script, it may not
run.

Best regards,

Haeyoon Cho.

2018-06-08 11:41 GMT+09:00 류정민 :

> Hi,
>
> my name is Jung Min You and I'm graduated course student in Sungkyunkwan
> University, South Korea.
>
> I followed your tutorial to study about gem5.
>
> For my research, I need to simulate the system using a gem5 full system
> mode.
>
> When I tried to run the fs mode, I used the script files located in
> gem5/configs/boot/~~.rcS.
>
> Meanwhile, to debug the result, I inserted some echo statement in the
> script file.
>
> However, no debug statement has printed in terminal.
>
> I tried to use hack_back_ckpt.rcS, and my command line as follows.
>
> build/X86/gem5.opt configs/example/fs.py --cpu-type="AtomicSimpleCPU"
> --caches --l1i_size=32kB --l1d_size=32kB --l2_size=2MB -F 2 -I
> 2 --kernel=$GEM5_DIR/system/binaries/x86_64-vmlinux-2.6.22.9.smp
> --disk-image=$GEM5_DIR/system/disks/linux-x86.img
> --script=configs/boot/hack_back_ckpt.rcS
>
> If there is any mistakes in my simulation progress, please tell me what is
> the problem.
>
> Best regards,
>
> Jung Min.
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

2018-06-05 Thread 조해윤
I found what is the problem.

The cause is not a dtb file. It is --mem-size.
You need to specify the unit of the capacity (MB or GB). As I think, it is
due to the lack of memory size.

2018-06-05 17:43 GMT+09:00 조해윤 :

> Dear Mitali Sinha.
>
> Sorry for late reply.
> Try it without specified dtb file in command line.
>
> Actually, I run moby by myself again before writing the reply.
>
> ./build/ARM/gem5.opt configs/example/fs.py --machine-type=RealViewPBX
> --os-type=android-ics --kernel=/dist/m5/system/
> binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
> --disk-image=/dist/m5/system/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
> --mem-size=256MB --script=/dist/m5/system/boot/adobe.rcS --frame-capture
>
> Although it is still booted up, there is no problem.
>
> Best Regards,
> Haeyoon Cho.
>
> 2018-06-03 22:13 GMT+09:00 Mitali Sinha :
>
>> @Haeyoon Cho sorry for late reply.
>>
>> I tried making the changes as follows:
>> gem5/configs/common/FSConfig.py:
>>  default_dtbs = {
>> "RealViewEB": None,
>> "RealViewPBX": None,
>> "VExpress_EMM": "armv7_gem5_v1_%dcpu.20170616.dtb" % num_cpus,
>> "VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
>> }
>>
>> default_kernels = {
>> "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8",
>> "RealViewPBX": "vmlinux.smp.ics.arm.asimbench.2.6.35",
>> "VExpress_EMM64": "vmlinux.aarch64.20140821",
>> }
>>
>> Then, I ran the following command:
>> build/ARM/gem5.opt configs/example/fs.py --os-type=android-ics
>> --machine-type=RealView_PBX --mem-size=512 --cpu-type=MinorCPU --caches
>> --disk-image=/home/sujay/gem5/full_system_asimbench/disks/AR
>> Mv7a-ICS-Android.SMP.Asimbench-v3.img --kernel=/home/sujay/gem5/full
>> _system_asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
>> --dtb-filename=/home/sujay/gem5/full_system_asimbench/binaries/armv7_gem5_v1_1cpu.dtb
>> --script=/home/sujay/gem5/full_system_asimbench/asimbench_
>> boot_scripts/adobe.rcS
>>
>> It gives the following error:
>> --- BEGIN LIBC BACKTRACE ---
>> build/ARM/gem5.opt(_Z15print_backtracev+0x28)[0xd99e78]
>> build/ARM/gem5.opt(_Z12abortHandleri+0x46)[0xdac9f6]
>> /lib/x86_64-linux-gnu/libpthread.so.0(+0x11390)[0x7f5eb6c93390]
>> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0x38)[0x7f5eb569b428]
>> /lib/x86_64-linux-gnu/libc.so.6(abort+0x16a)[0x7f5eb569d02a]
>> build/ARM/gem5.opt[0x939dcf]
>> build/ARM/gem5.opt[0x123ff36]
>> build/ARM/gem5.opt(_ZN8DRAMCtrl4initEv+0x20)[0x12626e0]
>> build/ARM/gem5.opt[0x11c065a]
>> build/ARM/gem5.opt[0xa224b7]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFra
>> meEx+0x6f55)[0x7f5eb6f4fe65]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCod
>> eEx+0x85c)[0x7f5eb708704c]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFra
>> meEx+0x6ffd)[0x7f5eb6f4ff0d]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCod
>> eEx+0x85c)[0x7f5eb708704c]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFra
>> meEx+0x6ffd)[0x7f5eb6f4ff0d]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCod
>> eEx+0x85c)[0x7f5eb708704c]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCod
>> e+0x19)[0x7f5eb6f48d99]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFra
>> meEx+0x613b)[0x7f5eb6f4f04b]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCod
>> eEx+0x85c)[0x7f5eb708704c]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFra
>> meEx+0x6ffd)[0x7f5eb6f4ff0d]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCod
>> eEx+0x85c)[0x7f5eb708704c]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCod
>> e+0x19)[0x7f5eb6f48d99]
>> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyRun_StringFl
>> ags+0x76)[0x7f5eb6fc31e6]
>> build/ARM/gem5.opt(_Z6m5MainiPPc+0x8f)[0xdab3ef]
>> build/ARM/gem5.opt(main+0x33)[0x8ba673]
>> /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf0)[0x7f5eb5686830]
>> build/ARM/gem5.opt(_start+0x29)[0x8f6e19]
>> --- END LIBC BACKTRACE ---
>> Aborted (core dumped)
>>
>>
>>
>> I don't know if I am doing it correctly. Also I am not sure if I am using
>> the correct dtb files and boot_emm.arm files that I have collected from
>> http://www.gem5.org/dist/current/arm/aarch-system-20180409.tar.xz.
>> <http://www.gem5.org/dist/current/arm/aarch-system-20180409.tar.xz>
&g

Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

2018-06-05 Thread 조해윤
 Dear Mitali Sinha.

Sorry for late reply.
Try it without specified dtb file in command line.

Actually, I run moby by myself again before writing the reply.

./build/ARM/gem5.opt configs/example/fs.py --machine-type=RealViewPBX
--os-type=android-ics
--kernel=/dist/m5/system/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=/dist/m5/system/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
--mem-size=256MB --script=/dist/m5/system/boot/adobe.rcS --frame-capture

Although it is still booted up, there is no problem.

Best Regards,
Haeyoon Cho.

2018-06-03 22:13 GMT+09:00 Mitali Sinha :

> @Haeyoon Cho sorry for late reply.
>
> I tried making the changes as follows:
> gem5/configs/common/FSConfig.py:
>  default_dtbs = {
> "RealViewEB": None,
> "RealViewPBX": None,
> "VExpress_EMM": "armv7_gem5_v1_%dcpu.20170616.dtb" % num_cpus,
> "VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
> }
>
> default_kernels = {
> "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8",
> "RealViewPBX": "vmlinux.smp.ics.arm.asimbench.2.6.35",
> "VExpress_EMM64": "vmlinux.aarch64.20140821",
> }
>
> Then, I ran the following command:
> build/ARM/gem5.opt configs/example/fs.py --os-type=android-ics
> --machine-type=RealView_PBX --mem-size=512 --cpu-type=MinorCPU --caches
> --disk-image=/home/sujay/gem5/full_system_asimbench/disks/
> ARMv7a-ICS-Android.SMP.Asimbench-v3.img --kernel=/home/sujay/gem5/
> full_system_asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
> --dtb-filename=/home/sujay/gem5/full_system_asimbench/
> binaries/armv7_gem5_v1_1cpu.dtb --script=/home/sujay/gem5/
> full_system_asimbench/asimbench_boot_scripts/adobe.rcS
>
> It gives the following error:
> --- BEGIN LIBC BACKTRACE ---
> build/ARM/gem5.opt(_Z15print_backtracev+0x28)[0xd99e78]
> build/ARM/gem5.opt(_Z12abortHandleri+0x46)[0xdac9f6]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x11390)[0x7f5eb6c93390]
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0x38)[0x7f5eb569b428]
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x16a)[0x7f5eb569d02a]
> build/ARM/gem5.opt[0x939dcf]
> build/ARM/gem5.opt[0x123ff36]
> build/ARM/gem5.opt(_ZN8DRAMCtrl4initEv+0x20)[0x12626e0]
> build/ARM/gem5.opt[0x11c065a]
> build/ARM/gem5.opt[0xa224b7]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f55)[
> 0x7f5eb6f4fe65]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[
> 0x7f5eb708704c]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[
> 0x7f5eb6f4ff0d]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[
> 0x7f5eb708704c]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[
> 0x7f5eb6f4ff0d]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[
> 0x7f5eb708704c]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_
> EvalCode+0x19)[0x7f5eb6f48d99]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x613b)[
> 0x7f5eb6f4f04b]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[
> 0x7f5eb708704c]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[
> 0x7f5eb6f4ff0d]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[
> 0x7f5eb708704c]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_
> EvalCode+0x19)[0x7f5eb6f48d99]
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyRun_StringFlags+0x76)[
> 0x7f5eb6fc31e6]
> build/ARM/gem5.opt(_Z6m5MainiPPc+0x8f)[0xdab3ef]
> build/ARM/gem5.opt(main+0x33)[0x8ba673]
> /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf0)[0x7f5eb5686830]
> build/ARM/gem5.opt(_start+0x29)[0x8f6e19]
> --- END LIBC BACKTRACE ---
> Aborted (core dumped)
>
>
>
> I don't know if I am doing it correctly. Also I am not sure if I am using
> the correct dtb files and boot_emm.arm files that I have collected from
> http://www.gem5.org/dist/current/arm/aarch-system-20180409.tar.xz.
> <http://www.gem5.org/dist/current/arm/aarch-system-20180409.tar.xz>
> image.
>
> Please help.
>
>
> On Tue, May 29, 2018 at 8:43 PM, 조해윤  wrote:
>
>> Dear Mitali Sinha.
>>
>> In my case, I run moby bench with RealView_PBX machine type.
>> I don't know if it is the cause, but give it a try.
>>
>> Best Regard,
>> Haeyoon Cho.
>>
>> 2018-05-29 20:39 GMT+09:00 Mitali Sinha :
>>
>>> I have followed the instructions provided in the gem5.org website to
>>> run the Moby benchmarks on gem5 as follows:
>>>
>>> 1.  Downloaded the Asimbench from https://bitbucket.org/yongbing
>&g

Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

2018-05-29 Thread 조해윤
Dear Mitali Sinha.

In my case, I run moby bench with RealView_PBX machine type.
I don't know if it is the cause, but give it a try.

Best Regard,
Haeyoon Cho.

2018-05-29 20:39 GMT+09:00 Mitali Sinha :

> I have followed the instructions provided in the gem5.org website to run
> the Moby benchmarks on gem5 as follows:
>
> 1.  Downloaded the Asimbench from https://bitbucket.org/
> yongbing_huang/asimbench/downloads/ which contains the following folders
> and files:
>  1.  asimbench_android_arm_kernel : vmlinux.smp.ics.arm.asimbench.
> 2.6.35
>  2.  asimbench_boot_scripts : contains the rcs scripts for
> different benchmarks
>  3.  asimbench_disk_image :  ARMv7a-ICS-Android.SMP.Asimbench-v3.img;
> sdcard-1g-mxplayer.img
>
> 2.  I have used the "armv7_gem5_v1_1cpu.dtb" and "boot_emm.arm" binaries
> downloaded from http://www.gem5.org/dist/current/arm/aarch-system-
> 20180409.tar.xz.
> 
>
> 3.  Made the following changes in the config/common/FSConfig.py :
>
> def makeArmSystem(..)
> .
> self.cf0 = CowIdeDisk(driveID='master')
> self.cf2 = CowIdeDisk(driveID='master')
> self.cf0.childImage(mdesc.disk())
> self.cf2.childImage(disk("sdcard-1g-mxplayer.img"))
> # Old platforms have a built-in IDE or CF controller. Default to
> # the IDE controller if both exist. New platforms expect the
> # storage controller to be added from the config script.
> if hasattr(self.realview, "ide"):
> #self.realview.ide.disks = [self.cf0]
> self.realview.ide.disks = [self.cf0, self.cf2]
> elif hasattr(self.realview, "cf_ctrl"):
> #self.realview.cf_ctrl.disks = [self.cf0]
> self.realview.cf_ctrl.disks = [self.cf0, self.cf2]
> else:
> self.pci_ide = IdeController(disks=[self.cf0])
> pci_devices.append(self.pci_ide)
> ...
>
> 4. Used the following command:
>
> build/ARM/gem5.opt configs/example/fs.py --os-type=android-ics
> --machine-type=VExpress_EMM --cpu-type=MinorCPU --caches
> --disk-image=/home/sujay/gem5/full_system_asimbench/disks/
> ARMv7a-ICS-Android.SMP.Asimbench-v3.img --kernel=/home/sujay/gem5/
> full_system_asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
> --dtb-filename=/home/sujay/gem5/full_system_asimbench/
> binaries/armv7_gem5_v1_1cpu.dtb --script=/home/sujay/gem5/
> full_system_asimbench/asimbench_boot_scripts/adobe.rcS
>
>
> 5. The above commands throw the following error:
>
>   ..
> Global frequency set at 1 ticks per second
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (512 Mbytes)
> info: kernel located at: /home/sujay/gem5/full_system_
> asimbench/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
> Listening for system connection on port 5900
> Listening for system connection on port 3456
> 0: system.remote_gdb: listening for remote gdb on port 7000
> info: Using bootloader at address 0x10
> info: Using kernel entry physical address at 0x80008000
> warn: DTB file specified, but no device tree support in kernel
>  REAL SIMULATION 
> warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
> info: Entering event queue @ 0.  Starting simulation...
>
> *warn: Device system.membus.badaddr_responder accessed by read to address
> 0x10009018 size=4fatal: Received error response packet for inst:
> 0/13.7/35/140.143 pc: 0x8003aba0 (ldr)*
> Memory Usage: 823816 KBytes
>
>
> Looking for some suggestion regarding successfully running the asimbench
> on gem5. Any help is appreciated. Thanks in advance.
>
>
> --
> Mitali Sinha,
> PhD Scholar,
> IIIT Delhi
>
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Re: [gem5-users] Terminating multi-core simulation

2018-05-27 Thread 조해윤
Dear Avais,

I think it is reasonable to normalize with the numbers of executed
instructions, but it still is a weakness that the running sections of
benchmarks are not same totally.
In my case, it was my best to exit the simulation by the total numbers of
executed instructions.
But if you can apply FIESTA methodology, it will be better.

Best Regards,
Haeyoon Cho.

2018-05-25 12:17 GMT+09:00 Muhammad Avais <avais.suh...@gmail.com>:

> Dear Haeyoon Cho.,
>
> I am really thankful to you for this help. Actually, i am not very good in
> modifying gem5 and this code will be very helpful for me.
>
> I have one more question, is it good idea to normalize the stats with
> number of instructions simulated to calculate energy or other things? Does
> people use this? Or some other metric to compare energy?
>
> Many thanks for your help,
> Best Regards,
> Avais
>
> On Thu, May 24, 2018 at 5:45 PM, 조해윤 <chohy2...@gmail.com> wrote:
>
>> Dear Avais,
>>
>> I think running workloads fairly is very important in multi-core
>> experiments, because the number of executed instructions of each core can
>> be changed depend on each experimental configuration.
>> There is a prior work how to experiment fairly on multi-core system; A.
>> Hilton et al., "FIESTA: A Sample-Balanced Multi-Program Workload
>> Methodology", MoBS, 2009.
>> However, implementing this methodology in gem5 is another problem, and I
>> couldn't do that.
>>
>> Alternatively, I modified the gem5 code to terminate by the number of
>> total executed instructions of all cores.
>> Existing gem5 code can only terminate by the maximum or minimum number of
>> executed instructions per core.
>> Since LocalSimLoopExitEvent() is called in CPU class in existing gem5
>> code, I modified system class code to correct the number of executed
>> instructions of all cores and to call LocalSimLoopExitEvent() by system
>> class.
>> As I think, the most important part is whether you can call
>> LocalSimLoopExitEvent() when you want.
>> I attach total_sim_exit.patch just for reference.
>> I modified followed six files.
>> /configs/commom/Simulation.py
>> /src/sim/system.hh
>> /src/sim/system.cc
>> /src/sim/System.py
>> /src/cpu/simple/base.hh
>> /src/cpu/o3/cpu.cc
>> This attached file may not compatible with current gem5 code, because I
>> modified code base on stable version of gem5 code.
>> Also, this modification is just for restrictive situation that one fast
>> forward and one real simulation, and coding style is not good.
>>
>> If you can modify gem5 code better than me, please let me know.
>>
>> Best Regards,
>> Haeyoon Cho.
>>
>>
>> 2018-05-23 15:55 GMT+09:00 Muhammad Avais <avais.suh...@gmail.com>:
>>
>>> Dear All,
>>>
>>>  I want to measure dynamic energy of L2 cache for multi-core
>>> simulations. For this purpose, i measure stats from gem5 like # of hits,  #
>>> of misses and # of writebacks.
>>>  As, multi-core simulation in gem5 terminates, as soon as, any
>>> workload reaches maximum count. Therefore, while comparing different
>>> schemes, each scheme terminates after different number of instructions, so
>>> stats like  # of hits,  # of misses and # of writebacks are not useful.
>>>Is there any  other metric that can be used to compare energy in
>>> multicore systems like weighted speed up for performance. Or is it possible
>>> that simulation always runs for fixed number of instruction.
>>>
>>> Many Thanks,
>>> Best Regards,
>>> Avais
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>>
>> ___
>> gem5-users mailing list
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>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
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> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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Re: [gem5-users] Terminating multi-core simulation

2018-05-24 Thread 조해윤
Dear Avais,

I think running workloads fairly is very important in multi-core
experiments, because the number of executed instructions of each core can
be changed depend on each experimental configuration.
There is a prior work how to experiment fairly on multi-core system; A.
Hilton et al., "FIESTA: A Sample-Balanced Multi-Program Workload
Methodology", MoBS, 2009.
However, implementing this methodology in gem5 is another problem, and I
couldn't do that.

Alternatively, I modified the gem5 code to terminate by the number of total
executed instructions of all cores.
Existing gem5 code can only terminate by the maximum or minimum number of
executed instructions per core.
Since LocalSimLoopExitEvent() is called in CPU class in existing gem5 code,
I modified system class code to correct the number of executed instructions
of all cores and to call LocalSimLoopExitEvent() by system class.
As I think, the most important part is whether you can call
LocalSimLoopExitEvent() when you want.
I attach total_sim_exit.patch just for reference.
I modified followed six files.
/configs/commom/Simulation.py
/src/sim/system.hh
/src/sim/system.cc
/src/sim/System.py
/src/cpu/simple/base.hh
/src/cpu/o3/cpu.cc
This attached file may not compatible with current gem5 code, because I
modified code base on stable version of gem5 code.
Also, this modification is just for restrictive situation that one fast
forward and one real simulation, and coding style is not good.

If you can modify gem5 code better than me, please let me know.

Best Regards,
Haeyoon Cho.


2018-05-23 15:55 GMT+09:00 Muhammad Avais :

> Dear All,
>
>  I want to measure dynamic energy of L2 cache for multi-core
> simulations. For this purpose, i measure stats from gem5 like # of hits,  #
> of misses and # of writebacks.
>  As, multi-core simulation in gem5 terminates, as soon as, any
> workload reaches maximum count. Therefore, while comparing different
> schemes, each scheme terminates after different number of instructions, so
> stats like  # of hits,  # of misses and # of writebacks are not useful.
>Is there any  other metric that can be used to compare energy in
> multicore systems like weighted speed up for performance. Or is it possible
> that simulation always runs for fixed number of instruction.
>
> Many Thanks,
> Best Regards,
> Avais
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>


tatal_sim_exit.patch
Description: Binary data
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Re: [gem5-users] how to compile hello.c of the linaro image with "Cross-Compile" and execute it in gem5.

2018-05-14 Thread 조해윤
First, cross compile hello.c. It is not dependent on gem5.

Second, mount the linaro image and copy the binary file.
For example,

mount -oloop,offset=32256 /tmp/linaro.img /mnt

Finally, run the FS simluation.
http://gem5.org/Running_gem5


2018-05-13 20:28 GMT+09:00 commerce _com :

> hi all;
>
> please help me I am beginner with gem5 ;
>
> how to compile hello.c of the linaro image with "Cross-Compile" and
> execute it in gem5.
>
> thanks;
>
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> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Re: [gem5-users] Is the dtb file important for FS simulation?

2018-03-06 Thread 조해윤
Thanks a lot.
It is great helpful to me.

2018-03-06 22:17 GMT+09:00 Ciro Santilli <ciro.santi...@gmail.com>:

> Ah, nevermind, I had forgotten this, the dtbs are tracked inside the gem5
> tree:
>
> https://github.com/gem5/gem5/blob/a66fe6a8c36c9ab49cb3a35065bfc6
> 45d51036c8/system/arm/dt/armv8.dts
>
> an built with:
>
> make -C system/arm/dt
>
> The Makefile uses the cpp preprocessor to generate the dtbs with
> different core counts:
> https://github.com/gem5/gem5/blob/a66fe6a8c36c9ab49cb3a35065bfc6
> 45d51036c8/system/arm/dt/Makefile#L48
>
> So hacking up that Makefile is another good option to get your dtbs.
>
> On Tue, Mar 6, 2018 at 10:55 AM, Ciro Santilli <ciro.santi...@gmail.com>
> wrote:
> > Yes, if you don't modify the dtb, the Linux kernel won't see the
> > change in the number of CPUs change, this can be verified with cat
> > /proc/cpuinfo.
> >
> > You can modify the dtb directly by first converting it to dts human
> > readable form: https://stackoverflow.com/questions/14000736/tool-to-
> visualize-the-device-tree-file-dtb-used-by-the-linux-
> kernel/39931834#39931834
> > and then doing the inverse operation.
> >
> > Normally the original source of the dts for ARM should be present on
> > the forked gem5 Linux kernel fork:
> > https://gem5.googlesource.com/arm/linux/+/917e007a4150d26a0aa95e4f5353ba
> 72753669c7/arch/arm/boot/dts/
> > but I can't find if easily for some reason, only
> > vexpress-v2p-ca15-tc1.dts, maybe someone can clarify their origin.
> >
> >
> > On Tue, Mar 6, 2018 at 10:46 AM, 조해윤 <chohy2...@gmail.com> wrote:
> >> Dear, everyone.
> >>
> >> I try to full system simulation for ARM ISA.
> >> So, I downloaded the pre-compiled kernels and disk images
> >> (aarch-system-20170616.tar.xz) from the repository
> >> (http://www.gem5.org/dist/current/arm/).
> >>
> >> There are several dtb files like below.
> >> vexpress-v2p-ca15-tc1-gem5_1cpus.20170616.dtb
> >> vexpress-v2p-ca15-tc1-gem5_2cpus.20170616.dtb
> >> vexpress-v2p-ca15-tc1-gem5_4cpus.20170616.dtb
> >>
> >> However, not for 8 or 16 cpus.
> >> If I want to experiment 16-cpu configuration, I should modify the dtb
> file?
> >>
> >> If I should modify the dtb file, how I can do that?
> >> I found the documentations to build a kernel or to make a disk image.
> >> http://gem5.org/ARM_Kernel
> >> http://gem5.org/Ubuntu_Disk_Image_for_ARM_Full_System
> >>
> >> But, I couldn't find any documentation to modify the dtb file.
> >> Is there any documentation for the dtb file?
> >>
> >> Best regards,
> >> Haeyoon Cho.
> >>
> >> ___
> >> gem5-users mailing list
> >> gem5-users@gem5.org
> >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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[gem5-users] Is the dtb file important for FS simulation?

2018-03-06 Thread 조해윤
Dear, everyone.

I try to full system simulation for ARM ISA.
So, I downloaded the pre-compiled kernels and disk images
(aarch-system-20170616.tar.xz) from the repository (
http://www.gem5.org/dist/current/arm/).

There are several dtb files like below.
vexpress-v2p-ca15-tc1-gem5_1cpus.20170616.dtb
vexpress-v2p-ca15-tc1-gem5_2cpus.20170616.dtb
vexpress-v2p-ca15-tc1-gem5_4cpus.20170616.dtb

However, not for 8 or 16 cpus.
If I want to experiment 16-cpu configuration, I should modify the dtb file?

If I should modify the dtb file, how I can do that?
I found the documentations to build a kernel or to make a disk image.
http://gem5.org/ARM_Kernel
http://gem5.org/Ubuntu_Disk_Image_for_ARM_Full_System

But, I couldn't find any documentation to modify the dtb file.
Is there any documentation for the dtb file?

Best regards,
Haeyoon Cho.
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Re: [gem5-users] Configuration visualizer

2018-01-03 Thread 조해윤
Dear, Timon

Install pydot, and then rebuild gem5 and run simulation.
Then, you can see config.dot.pdf file which has the content like below.
[image: 본문 이미지 1]

Best regards

Haeyoon Cho

2018-01-03 23:06 GMT+09:00 Timon Evenblij :

> Hi all,
>
> I thought I once came across a tool to visualize the configuration used
> for a simulation in gem5, but I didn't look into it at the moment. Right
> now, this would be very useful, especially to visualize the configuration
> used for the memory hierarchy (i.e. how all memory objects are connected
> with all the ports). However, I cannot seem to find it. Did I misunderstood
> that such a tool exists, or can somebody point me into the right direction
> where to find it?
>
> Otherwise, I would perhaps create a tool like that, so any tips or
> pitfalls are welcome as well.
>
> Best regards
>
> Timon
>
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Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache

2017-12-05 Thread 조해윤
Dear, Varun.

In my opinion, you can make new class which inherit BaseCache or MemObject.

As I think, if you implement tag-less cache in conventional cache class,
you need to a flag which indicate tag-less cache and many conditional
sentence everywhere operate differently with a conventional cache.
It may be also less readable code.

But if you make new class, you can write the code for tag-less cache
totally.
Make a new class and copy the code of the conventional cache. If you
inherit MemObject, copy BaseCache code also.
After copy them, modify for tag-less cache.

Cheers,
Haeyoon Cho.

2017-12-06 16:27 GMT+09:00 Saivarun R :

> Hi,
>
> I'm trying to implement a tag-less cache architecture only for the last
> level cache. As I understand, there is only one implementation for all
> levels of caches. How do I change only the implementation for the last
> level cache, leaving other caches being accessed in a conventional manner.
>
> Any help is deeply appreciated :-)
>
> Thank you in advance
> Varun
>
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[gem5-users] The learning gem5 code can't be compiled.

2017-12-04 Thread 조해윤
Hi all,

The recent commit for learning gem5 occurs a compile error.

The cause is #include base/misc.hh, because misc.hh is renamed to
logging.hh recently.
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[gem5-users] How can I use Write Through Cache

2017-11-23 Thread 조해윤
Hi all,

I have two questions.

First, as I know, in gem5, there is only write-back cache. Is it alright?

Second, if there is only write-back cache, for implementation, how can I
approach to implement a write-through cache?

Thanks.

Haeyoon Cho
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[gem5-users] Read error, exit when run mcf of spec2006

2017-11-14 Thread 조해윤
Hi all,

I am trying to test my new cache scheme in gem5, but when I try to run the
429.mcf of spec2006, there is a error to load a file (maybe inp.in).
The other benchmarks of spec2006 are run well.

I saw the similar previous case in the below link.
http://thread.gmane.org/gmane.comp.emulators.m5.users/17104
But there isn't the solution.

Is there anyone know about this?
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Re: [gem5-users] Small entry table creation in gem5

2017-10-11 Thread 조해윤
Hello.

I think it depends on the purpose of the table and modeling features.

For example,  let's look a cache tag modeling case.
BaseTags class (/mem/cache/tags/base.hh), which is a kind of table to store
tags, inherits the ClockedObject, because BaseTags needs to model the clock
latency.
However, Cacheset class (/mem/cache/tags/cacheset.hh), which is used in
BaseSetAssoc (it inherits BaseTags class), doesn't inherit any class.
Because, Cacheset is just a data structure, which doesn't model clock
latency.
The latency to access Cacheset (it sounds wired actually, because latency
is for tag access and Cacheset is subset of tag model) is modeled in
BaseSetAssoc class, which inherits ClockedObject.

Haeyoon Cho

2017-10-10 13:17 GMT+09:00 Muhammad Avais :

> Hi,
>
> I want to create small table (256 entries) in gem5 that is accessed on
> each cache miss and follows LRU replacement policy.
>
> Can someone guide me how to do it? (Which classes i should use or inherit)
>
> Many Thanks
>
> Avais
>
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[gem5-users] Is the gem5 stable version supported continuously?

2017-08-28 Thread 조해윤
As I see, the latest stable version is 2015.09.03.

And it is very different with recently public gem5.

Is the gem5 stable version supported continuously?

If not, and I need to use recent public gem5, could it be problem due to
frequent code change?
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[gem5-users] What is the requirement for cache?

2017-02-20 Thread 조해윤
Dear all,

I'm trying to make my own cache object, which is finally used to simulate
the DRAM Cache using DRAMSim2.

This is my first time to modify gem5 code, so I have tried to make a simple
cache block to satisfy essential functions for a cache.
And I saw the tutorials and the sample code of Jason Lowe-Power.
http://learning.gem5.org/book/part2/simplecache.html

So I plan to extend this sample code for my purpose.
However, when I use this simple cache with existed gem5 cache block, gem5
makes a error.

I tested this simple cache in 3 case using se.py.
I replaced the below part in CacheConfig.py to simple cache which is
L1_DSimple, L1_ISimple, L2_Simple.
[image: 본문 이미지 1]

and run it in 2 different ISA. ( cmd was hello in test-progs )

ISA

L1_DSimple

L1_ISimple

(1-level cache hierarchy)

L1_DSimple

L1_ISimple

L2_Simple

L1_DCache

L1_ICache

L2_Simple

X86

Working well

Working well

gem5.opt: build/X86/mem/packet.hh:847: void Packet::makeResponse():
Assertion `needsResponse()' failed.

ARM

gem5.opt: build/ARM/mem/request.hh:674: uint64_t Request::getExtraData()
const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)' failed.

gem5.opt: build/ARM/mem/request.hh:674: uint64_t Request::getExtraData()
const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)' failed.

gem5.opt: build/ARM/mem/packet.hh:847: void Packet::makeResponse():
Assertion `needsResponse()' failed.

When I read the sample code of Jason Lowe-Power, I think this cache has
essential functions for cache.
But it doesn't work well with exited gem5 cache block.
What is the problem?

Best regards.
HaeYoon Cho
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