Hi gem5 community,
Any suggestions on this topic?
On Thu, May 27, 2021 at 11:29 AM Chongzhi Zhao wrote:
> Update:
> To enforce strict inclusivity, I changed BaseCache::handleEvictions() to
> below (changes in bold font). I also added "fully_incl" to Enum in
> Cache.py.
> Would this make caches
Update:
To enforce strict inclusivity, I changed BaseCache::handleEvictions() to
below (changes in bold font). I also added "fully_incl" to Enum in
Cache.py.
Would this make caches strictly inclusive by back invalidation upon
eviction?
bool
BaseCache::handleEvictions(std::vector _blks,
Hi gem5 community,
TL;DR:
1. In "classic" memory, the current 2 options, mostly_incl and
mostly_excl, seem to apply only to cache fill but NOT eviction. As a
result, blocks evicted from L2 may be still present in L1. Is my
understanding correct?
2. What would be a reasonable way
The problem seems to be caused by the m5.cpt in the checkpoint I acquired
not having arm-sve tag and vecPredRegs. However, if I run cpt_upgrader.py
on the checkpoint, it adds the arm-sve tag without doing anything about the
absence of vecPredRegs. Does anyone know a workaround without reverting my
To further clarify, I did run util/cpt_upgrader.py on the checkpoint to
no avail.
*Chongzhi Zhao*
On Tue, Nov 17, 2020 at 1:51 PM Chongzhi Zhao wrote:
> Hi,
>
> I attempted to recover some Simpoint checkpoints for x86 in SE mode and
> got the error below. I did see the warning on using
Hi,
I attempted to recover some Simpoint checkpoints for x86 in SE mode and got
the error below. I did see the warning on using util/cpt_upgrader.py but am
not sure if they are related. I also reverted my gem5 to v19.0.0, but the
error persisted. Has anyone seen this before?
Command:
Hi,
I'm trying to evaluate a cache replacement policy with classic memory in SE
mode. A few questions:
1. The policy requires PC, address, and access type (demand
read/writeback/prefetch) to be made visible. However, I don't see these
exposed to the replacement policies. Where may I find
Hi,
I'm running FS simulation with TimingSimpleCPU. I noticed via htop that
the simulation is very heavy on a single host core but not utilizing
others. Then I looked it up but merely found this ancient page:
http://www.m5sim.org/Parallel_M5 . What's the current status of this
matter? Is there
The new method is here:
https://www.gem5.org/documentation/general_docs/m5ops/
*Chongzhi "Paul" Zhao*
Doctoral Student in Computer Engineering
Texas A University
Email: chongzhizhao4 (at) gmail (dot) com
On Fri, Aug 21, 2020 at 12:44 PM Abhishek Singh via gem5-users <
gem5-users@gem5.org>
Hi Jaspinder,
What you observed is consistent with this post:
https://www.gem5.org/documentation/benchmark_status/
The common advice is usually that you boot with AtomicSimpleCPU, make a
checkpoint, and then restore the checkpoint with a more detailed CPU model.
Sincerely,
*Chongzhi "Paul" Zhao*
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