[gem5-users] Re: MSI Protocol at Memory
Not sure about this, but I have looked at MOESI_CMP_Directory as it supports sharing/owning in clusters. Maybe you can think of directory, and L1, L2 as a three level system and get inspiration from there. Thanks and Regards, Gautam Pathak David R. Cheriton School of Computer Science University of Waterloo From: Arteen Abrishami via gem5-users Sent: Wednesday, October 11, 2023 6:06 AM To: The gem5 Users mailing list Cc: Arteen Abrishami Subject: [gem5-users] MSI Protocol at Memory Hello everyone I’m an undergraduate student and going to embark on a journey to extend the protocol for MESI_Three_Level at the memory level to MSI or MESI, as opposed to the two-state MI that it is right now. Does anyone have any tips or advice for this journey, perhaps one of you has done something similar or already have this implemented? I understand that at a minimum, this requires modifying both the memory SLICC protocol and also the last level cache. Thanks a lot, Arteen UCLA ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Query regarding l1 load hit time
Hi, I am trying to set accurate latency numbers for my test system, and I noticed a weird thing happening in the logs. My system.clk_domain.clock is 1000 so that should mean 1000 ticks equal to 1 cycle. I noticed that the time it takes for LD to finish is (4761575500−4761566500) which is 9000 ticks i.e. 9 cycles, but the debug print says that it took 18 cycles. Am I missing something here? It would be great if someone could clarify on this. [image] Thanks and Regards, Gautam ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Ruby_mem_test.py dma test bug
Hi Gabriel, Sorry, but I am confused. I recompiled with the changes and also set percent_uncacheable = 100 for the DMA controller. It still shows the same error. Also, isn't DMA supposed to work coherently with the protocol? Otherwise couldn't we simply read or write without worrying about coherency in uncacheable accesses? Line 86 of ruby_mem_test also says that ruby does not support atomic or uncacheable accesses. I am trying to make changes to a protocol in order for it to support dma operations and was hoping I could speed up the checking process by using ruby_mem_test rather than waiting for hours for fs.py to boot up everytime. Thanks and Regards, Gautam Pathak David R. Cheriton School of Computer Science University of Waterloo From: gabriel.bus...@arteris.com Sent: Tuesday, September 27, 2022 2:06 AM To: gem5-users@gem5.org Subject: [gem5-users] Re: Ruby_mem_test.py dma test bug Hi Gautam, I believe this is caused by a failing dice rolling on line memtest.cc:223. Replace: bool uncacheable = random_mt.random(0, 100) < percentUncacheable; with bool uncacheable = random_mt.random(1, 100) <= percentUncacheable; I forgot to push that patch, my mistake. Explanation: DMAs should be emulated by MemTest by sending 100% uncachable accesses. The offending line causes the DMA MemTest to send a coherent access ~1% of the time although configured with percent_uncacheable == 100. These 1% accesses then target the same memory region as the coherent CPU (cache) accesses but it is handled as a DMA (non-coherent) access by Ruby. And there you get that error that merely tells you that an unexpected value was read by MemTest. Best, Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Ruby_mem_test.py dma test bug
I was trying to test DMA using ruby_mem_test.py and noticed that the following command: ./build/X86/gem5.opt configs/example/ruby_mem_test.py --num-dmas 1 throws the error: AttributeError: object 'MemTest' has no attribute 'test' (C++ object is not yet constructed, so wrapped C++ methods are unavailable.) At: build/X86/python/m5/SimObject.py(851): __getattr__ configs/example/ruby_mem_test.py(137): build/X86/python/m5/main.py(589): main So, I looked at the MemTest.py object file and tried the next best thing, replacing ".test" by ".port" as port was defined as a RequestPort and there was no "test" member variable. Is this a valid error? Also, when I run again with dma.port instead of dma.test on line ruby_mem_test.py:137, the test seems to run only to say that dma isn't working correctly: build/X86/cpu/testers/memtest/memtest.cc:162: panic: system.dma_devices: read of 105e01 (blk 105e00) @ cycle 5199 returns 0, expected fc Memory Usage: 771852 KBytes Program aborted at tick 5199 --- BEGIN LIBC BACKTRACE -- I still don't exactly understand what is going on exactly.. I think that the right kind of object might not be getting set as a parameter in dma_ports for create_system. On the other hand, this test was for MESI_Two_Level for which DMA should be working as it boots up in Full System mode. Thanks, Gautam ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Trying to add barrier to threads example
Hi Prof. Jason, Thank you for the clarification. I further wanted to ask whether there is any other way to do multithreaded application tests correctly in SE+ruby mode? If not, then we'll be forced to use FS mode which afaik does not work currently with MSI (our modified protocol will have to be changed again because FS mode requires (?) DMA support). Do you have any advice for things to watch out for while testing our multithreaded applications in Full System mode? Thanks and Regards, Gautam Pathak From: Jason Lowe-Power Sent: Friday, September 2, 2022 10:51 AM To: The gem5 Users mailing list Subject: [gem5-users] Re: Trying to add barrier to threads example Hi Gautam, Functional accesses (i.e., fake/debug accesses that bypass all timing) and Ruby do not play well together. Fundamentally, it is hard to know what is the most up to date value or which value(s) you have to update when a cache block is in an intermediate state. With MI_example and MESI, these protocols probably have more support for functional reads than MSI, but you're also just getting lucky with those. At some point, if you're doing functional accesses, it's going to fail. In SE mode, to implement the fake system calls which execute *in the simulator* instead of via the guest kernel executing on the simulated CPU, we must use the fake/unrealistic/magic functional accesses. So, this is why SE mode + multithreading + Ruby will almost always run into a problem at some point. FS mode will not have this issue because it does not use functional accesses (almost none at all) and nothing is "faked." The simulated CPU executes all of the kernel system calls. Hopefully this answers your question. Let me know if I can provide more info :) Cheers, Jason On Thu, Sep 1, 2022 at 3:58 PM Gautam Pathak mailto:gautam.pat...@uwaterloo.ca>> wrote: Hi All, I'm trying to add a custom thread barrier to the array_add function by using __sync_fetch_and_add. The system I'm using is MSI using Ruby in SE mode. When I run this, I get the following error: build/X86/mem/ruby/system/RubyPort.cc:434: fatal: Ruby functional read failed for address 0x15b918. Till now I have observed that there is an open issue which mentions that Ruby+multithreading+SE is not supported. The exact fault occurs in Futex syscall. (Ref. https://gem5.atlassian.net/browse/GEM5-676). However, I have tested the same for MI_Example protocol (using simple_ruby.py) and MESI_Two_Level (using se.py) upto 30+ threads and it works. This makes me wonder whether this is an MSI protocol bug. Any suggestions on how I should go on about this issue would be appreciated! Otherwise, is Full System mode the recommended option for Ruby+custom coherence protocol+multithreading (possibly using atomics)? Thanks and Regards, Gautam Pathak ___ gem5-users mailing list -- gem5-users@gem5.org<mailto:gem5-users@gem5.org> To unsubscribe send an email to gem5-users-le...@gem5.org<mailto:gem5-users-le...@gem5.org> ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Trying to add barrier to threads example
Hi All, I'm trying to add a custom thread barrier to the array_add function by using __sync_fetch_and_add. The system I'm using is MSI using Ruby in SE mode. When I run this, I get the following error: build/X86/mem/ruby/system/RubyPort.cc:434: fatal: Ruby functional read failed for address 0x15b918. Till now I have observed that there is an open issue which mentions that Ruby+multithreading+SE is not supported. The exact fault occurs in Futex syscall. (Ref. https://gem5.atlassian.net/browse/GEM5-676). However, I have tested the same for MI_Example protocol (using simple_ruby.py) and MESI_Two_Level (using se.py) upto 30+ threads and it works. This makes me wonder whether this is an MSI protocol bug. Any suggestions on how I should go on about this issue would be appreciated! Otherwise, is Full System mode the recommended option for Ruby+custom coherence protocol+multithreading (possibly using atomics)? Thanks and Regards, Gautam Pathak ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Difference between configs/ruby scripts vs. learning_gem5/part3 config scripts
Hi, Can anyone please tell me the difference between config scripts for coherence protocols present in configs/ruby vs. those that are used by simple_ruby.py? For example, ruby_caches_MI_example.py can be used by simple_ruby.py to simulate a simple MI protocol. However, configs/ruby/MI_example.py is also present (which I don't know how to use). As far as I can see, they are quite different in terms of class hierarchy (for eg. one sets up a MyCacheSystem whereas the other defines two functions define_options and create_system). Also, in one L1Cache inherits from RubyCache whereas the other inherits from L1Cache_Controller. Any clarification would be appreciated. My main goal is to use and understand how the ruby testing framework scripts work with different coherence protocols (ruby_random_test, ruby_test, ruby_direct_test). Any help would be appreciated! Thanks and Regards, Gautam Pathak ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Adding debug ROI to test application
Hi, Thanks for the help! It works great. Thanks and Regards, Gautam From: Hoa Nguyen Sent: Wednesday, June 8, 2022 2:51 AM To: The gem5 Users mailing list Subject: [gem5-users] Re: Adding debug ROI to test application Hi, I think there are a couple of options. One way is to do m5_exit() right before the ROI, record the current Tick, and rerun with --debug-start set to that number. Another way is that, in the first run, you can do m5_exit() right before the ROI, then take a checkpoint. In the next run, you can enable the debug flags (and restore the checkpoint). Regards, Hoa Nguyen On Tue, Jun 7, 2022, 15:53 Gautam Pathak mailto:gautam.pat...@uwaterloo.ca>> wrote: Hi, Is there any way to only trace certain specific areas of interest in test application? I am currently using --debug-start and --debug-end but it is very difficult to find the exact time when region of interest is executed. Also, I looked at m5_work_begin() and m5_work_end() but that seems to be for a different thing altogether. Thanks and Regards, Gautam ___ gem5-users mailing list -- gem5-users@gem5.org<mailto:gem5-users@gem5.org> To unsubscribe send an email to gem5-users-le...@gem5.org<mailto:gem5-users-le...@gem5.org> ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Adding debug ROI to test application
Hi, Is there any way to only trace certain specific areas of interest in test application? I am currently using --debug-start and --debug-end but it is very difficult to find the exact time when region of interest is executed. Also, I looked at m5_work_begin() and m5_work_end() but that seems to be for a different thing altogether. Thanks and Regards, Gautam ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
