[gem5-users] How to create a packet to do MemRef without segment fault?

I create a packet by using constructor of class Request and Packet. But when sending it in memory error will occur. Is there something important I miss? Thanks. ___ gem5-users mailing list gem5-users@gem5.org

[gem5-users] How to change Timing access into Functional access?

Hi all, Is there a way to make some load/store to take into effect immediately like functional access, where should i change the source code? ISA description or CPU/LSQ ? Thanks. ___ gem5-users mailing list gem5-users@gem5.org

Re: [gem5-users] pause while running on riscv

use relative paths, as they don't always resolve to what > I expect depending on where I'm running gem5 from. > > On Sun, Apr 15, 2018 at 5:14 AM, IL Ne <nedni...@gmail.com> wrote: > >> Hello, >> I wrote a c++ file, and compile it by using riscv-g++ with -std=c++11 >

[gem5-users] pause while running on riscv

Hello, I wrote a c++ file, and compile it by using riscv-g++ with -std=c++11 This program involves file stream. While running by gem5, the process will pause. I check insts with debug flags, finding that output paused at somewhere like this below: 34489000: system.cpu T0 : @_read: c_addi sp,

[gem5-users] Is it a way to change the behavior of "load" and "store"?

Hi, I know that dealing with memory instruction is complicated, which involves things like iew, lsq. In my work, I want to make the memory access process to be accomplished instantaniously, meanwhile functional simulation should still be right. For example, Macroop ADD contains microops like