[gem5-users] Re: HPCG on RISCV

2022-10-07 Thread Jason Lowe-Power
506572
> >> > ITER: 1 | i: 7 | j: 3 Result(i: 2.645751 | j: 1.732051 | i*j:
> >> > 4.582576): 220.089147
> >> > ITER: 1 | i: 7 | j: 4 Result(i: 2.645751 | j: 2.00 | i*j:
> >> > 5.291503): 225.380650
> >> > ITER: 1 | i: 7 | j: 5 Result(i: 2.645751 | j: 2.236068 | i*j:
> >> > 5.916080): 231.296730
> >> > ITER: 1 | i: 7 | j: 6 Result(i: 2.645751 | j: 2.449490 | i*j:
> >> > 6.480741): 237.777470
> >> > ITER: 1 | i: 7 | j: 7 Result(i: 2.645751 | j: 2.645751 | i*j:
> >> > 7.00): 244.777470
> >> > ITER: 1 | i: 7 | j: 8 Result(i: 2.645751 | j: 2.828427 | i*j:
> >> > 7.483315): 252.260785
> >> > ITER: 1 | i: 7 | j: 9 Result(i: 2.645751 | j: 3.00 | i*j:
> >> > 7.937254): 260.198039
> >> > ITER: 1 | i: 8 | j: 0 Result(i: 2.828427 | j: 0.00 | i*j:
> >> > 0.00): 260.198039
> >> > ITER: 1 | i: 8 | j: 1 Result(i: 2.828427 | j: 1.00 | i*j:
> >> > 2.828427): 263.026466
> >> > ITER: 1 | i: 8 | j: 2 Result(i: 2.828427 | j: 1.414214 | i*j:
> >> > 4.00): 267.026466
> >> > ITER: 1 | i: 8 | j: 3 Result(i: 2.828427 | j: 1.732051 | i*j:
> >> > 4.898979): 271.925446
> >> > ITER: 1 | i: 8 | j: 4 Result(i: 2.828427 | j: 2.00 | i*j:
> >> > 5.656854): 277.582300
> >> > ITER: 1 | i: 8 | j: 5 Result(i: 2.828427 | j: 2.236068 | i*j:
> >> > 6.324555): 283.906855
> >> > ITER: 1 | i: 8 | j: 6 Result(i: 2.828427 | j: 2.449490 | i*j:
> >> > 6.928203): 290.835059
> >> > ITER: 1 | i: 8 | j: 7 Result(i: 2.828427 | j: 2.645751 | i*j:
> >> > 7.483315): 298.318373
> >> > ITER: 1 | i: 8 | j: 8 Result(i: 2.828427 | j: 2.828427 | i*j:
> >> > 8.00): 306.318373
> >> > ITER: 1 | i: 8 | j: 9 Result(i: 2.828427 | j: 3.00 | i*j:
> >> > 8.485281): 314.803655
> >> > ITER: 1 | i: 9 | j: 0 Result(i: 3.000000 | j: 0.00 | i*j:
> >> > 0.00): 314.803655
> >> > ITER: 1 | i: 9 | j: 1 Result(i: 3.00 | j: 1.00 | i*j:
> >> > 3.00): 317.803655
> >> > ITER: 1 | i: 9 | j: 2 Result(i: 3.00 | j: 1.414214 | i*j:
> >> > 4.242641): 322.046295
> >> > ITER: 1 | i: 9 | j: 3 Result(i: 3.00 | j: 1.732051 | i*j:
> >> > 5.196152): 327.242448
> >> > ITER: 1 | i: 9 | j: 4 Result(i: 3.00 | j: 2.00 | i*j:
> >> > 6.00): 333.242448
> >> > ITER: 1 | i: 9 | j: 5 Result(i: 3.00 | j: 2.236068 | i*j:
> >> > 6.708204): 339.950652
> >> > ITER: 1 | i: 9 | j: 6 Result(i: 3.00 | j: 2.449490 | i*j:
> >> > 7.348469): 347.299121
> >> > ITER: 1 | i: 9 | j: 7 Result(i: 3.00 | j: 2.645751 | i*j:
> >> > 7.937254): 355.236375
> >> > ITER: 1 | i: 9 | j: 8 Result(i: 3.00 | j: 2.828427 | i*j:
> >> > 8.485281): 363.721656
> >> > ITER: 1 | i: 9 | j: 9 Result(i: 3.00 | j: 3.00 | i*j:
> >> > 9.00): 372.721656
> >> > Final Result: 372.721656
> >> >
> >> >
> >> >
> >> > As we can see in the following iterations the sqrt(1) as well as the
> >> > result is set to zero for some reason.
> >> >
> >> > ITER: 0 | i: 1 | j: 4 Result(i: 0.00 | j: 2.00 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 5 Result(i: 0.00 | j: 2.236068 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 6 Result(i: 0.00 | j: 2.449490 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 7 Result(i: 0.00 | j: 2.645751 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 8 Result(i: 0.00 | j: 2.828427 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 9 Result(i: 0.00 | j: 3.00 | i*j:
> >> > 0.00): 0.00
> >> >
> >> > Please help me to resolve the accuracy issue! I think that it will
> >> > be very useful for gem5 community.
> >> >
> >> > To be noticed, I find the correct simulated tick in which the
> >> > application started in FS (using m5 dumpstats), and I start the
> >> > --debug-start, but the trace file which is generated is 10x larger
> >> > than SE mode for the same application. How can I compare them?
> >> >
> >> > Thank you in advance!
> >> > Best regards,
> >> > Nikos
> >> >
> >> > Quoting Νικόλαος Ταμπουρατζής :
> >>

[gem5-users] Re: HPCG on RISCV

2022-09-21 Thread Jason Lowe-Power
Hi Nikos,

You can use --debug-start to start the debugging after some number of
ticks. Also, I would expect that the difference should come up quickly, so
no need to run the program to the end.

For the FS mode one, you will want to just start the trace as the
application starts. This could be a bit of a pain.

I'm not really sure what fundamentally could be different. FS and SE mode
use the exact same code for executing instructions, so I don't think that's
the problem. Have you tried running for smaller inputs or just one
iteration?

Jason



On Wed, Sep 21, 2022 at 9:04 AM Νικόλαος Ταμπουρατζής <
ntampourat...@ece.auth.gr> wrote:

> Dear Bobby,
>
> Iam trying to add --debug-flags=Exec (building the gem5 for gem5.opt
> not for gem5.fast which I had) but the debug traces exceed the 20GB
> (and it is not finished yet) for less than 1 simulated second. How can
> I reduce the size of the debug-flags (or set something more specific)?
>
> In contrast I build the HPCG benchmark with DHPCG_DEBUG flag. If you
> want, you can compare these two output files
> (hpcg20010909T014640_SE_Mode & HPCG-Benchmark_3.1_FS_Mode). As you can
> see, something goes wrong with the accuracy of calculations in FS mode
> (benchmark uses double precission). You can find the files here:
> http://kition.mhl.tuc.gr:8000/d/68d82f3533/
>
> Best regards,
> Nikos
>
> Quoting Jason Lowe-Power :
>
> > That's quite odd that it works in SE mode but not FS mode!
> >
> > I would suggest running with --debug-flags=Exec for both and then
> perform a
> > diff to see how they differ.
> >
> > Cheers,
> > Jason
> >
> > On Tue, Sep 20, 2022 at 2:45 PM Νικόλαος Ταμπουρατζής <
> > ntampourat...@ece.auth.gr> wrote:
> >
> >> Dear Bobby,
> >>
> >> In QEMU I get the same (correct) results that I get in SE mode
> >> simulation. I get invalid results in FS simulation (in both
> >> riscv-fs.py and riscv-ubuntu-run.py). I cannot access real RISCV
> >> hardware at this moment, however, if you want you may execute my xhpcg
> >> binary (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/) with the
> >> following configuration:
> >>
> >> ./xhpcg --nx=16 --ny=16 --nz=16 --npx=1 --npy=1 --npz=1 --rt=0.1
> >>
> >> Please let me know if you have any updates!
> >>
> >> Best regards,
> >> Nikos
> >>
> >>
> >> Quoting Jason Lowe-Power :
> >>
> >> > Hi Nikos,
> >> >
> >> > I notice you said the following in your original email:
> >> >
> >> > In addition, I used the RISCV Ubuntu image
> >> >> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu
> ),
> >> >> I installed the gcc compiler, compile it (through qemu) and I get
> >> >> wrong results too.
> >> >
> >> >
> >> > Is this saying you get the wrong results is QEMU? If so, the bug is in
> >> GCC
> >> > or the HPCG workload, not in gem5. If not, I would test in QEMU to
> make
> >> > sure the binary works there. Another way you could test to see if the
> >> > problem is your binary or gem5 would be to run it on real hardware. We
> >> have
> >> > access to some RISC-V hardware here at UC Davis, if you don't have
> access
> >> > to it.
> >> >
> >> > Cheers,
> >> > Jason
> >> >
> >> > On Tue, Sep 20, 2022 at 12:58 AM Νικόλαος Ταμπουρατζής <
> >> > ntampourat...@ece.auth.gr> wrote:
> >> >
> >> >> Dear Bobby,
> >> >>
> >> >> 1) I use the original riscv-fs.py which is provided in the latest
> gem5
> >> >> release.
> >> >> I run the gem5 once (./build/RISCV/gem5.fast -d ./HPCG_FS_results
> >> >> ./configs/example/gem5_library/riscv-fs.py) in order to download the
> >> >> riscv-bootloader-vmlinux-5.10 and riscv-disk-img.
> >> >> After this I mount the riscv-disk-img (sudo mount -o loop
> >> >> riscv-disk-img /mnt), put the xhpcg executable and I do the following
> >> >> changes in riscv-fs.py to boot the riscv-disk-img with executable:
> >> >>
> >> >> image = CustomDiskImageResource(
> >> >>  local_path = "/home/cossim/.cache/gem5/riscv-disk-img",
> >> >> )
> >> >>
> >> >> # Set the Full System workload.
> >> >> board.set_kernel_disk_workload(
> >> >> kernel=Resource("riscv-bootloader-vmlinux-5.10&qu

[gem5-users] Re: 3D NoC and Routerless NoC support in gem5

2022-09-21 Thread Jason Lowe-Power
Hi Ali,

For a 3D mesh, you'll have to create your own topology. This video should
be helpful in explaining how to do that: https://youtu.be/rZ-AYaKBK4M

For the most recent updates to the network models, you can see information
on HeteroGarnet: https://www.gem5.org/2020/05/27/heterogarnet.html

Cheers,
Jason

On Wed, Sep 21, 2022 at 12:37 AM Ali Karazmoodeh 
wrote:

> Hello,
> I am new to gem5 and I want to simulate a 3D Mesh in Heterogarnet. I was
> wondering if there is a standard 3D Mesh topology file to build upon it and
> continue my work from there, or if each researcher needs to create their 3D
> topology from the 2D counterparts.
> Moreover, in the paper "The gem5 simulator: version 20.0+", it is
> mentioned that work is in progress to include support for routerless NoCs
> in the gem5 simulator. Where can I find this work?
>
> Sincerely yours,
> Ali Karazmoodeh.
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: HPCG on RISCV

2022-09-20 Thread Jason Lowe-Power
That's quite odd that it works in SE mode but not FS mode!

I would suggest running with --debug-flags=Exec for both and then perform a
diff to see how they differ.

Cheers,
Jason

On Tue, Sep 20, 2022 at 2:45 PM Νικόλαος Ταμπουρατζής <
ntampourat...@ece.auth.gr> wrote:

> Dear Bobby,
>
> In QEMU I get the same (correct) results that I get in SE mode
> simulation. I get invalid results in FS simulation (in both
> riscv-fs.py and riscv-ubuntu-run.py). I cannot access real RISCV
> hardware at this moment, however, if you want you may execute my xhpcg
> binary (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/) with the
> following configuration:
>
> ./xhpcg --nx=16 --ny=16 --nz=16 --npx=1 --npy=1 --npz=1 --rt=0.1
>
> Please let me know if you have any updates!
>
> Best regards,
> Nikos
>
>
> Quoting Jason Lowe-Power :
>
> > Hi Nikos,
> >
> > I notice you said the following in your original email:
> >
> > In addition, I used the RISCV Ubuntu image
> >> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu),
> >> I installed the gcc compiler, compile it (through qemu) and I get
> >> wrong results too.
> >
> >
> > Is this saying you get the wrong results is QEMU? If so, the bug is in
> GCC
> > or the HPCG workload, not in gem5. If not, I would test in QEMU to make
> > sure the binary works there. Another way you could test to see if the
> > problem is your binary or gem5 would be to run it on real hardware. We
> have
> > access to some RISC-V hardware here at UC Davis, if you don't have access
> > to it.
> >
> > Cheers,
> > Jason
> >
> > On Tue, Sep 20, 2022 at 12:58 AM Νικόλαος Ταμπουρατζής <
> > ntampourat...@ece.auth.gr> wrote:
> >
> >> Dear Bobby,
> >>
> >> 1) I use the original riscv-fs.py which is provided in the latest gem5
> >> release.
> >> I run the gem5 once (./build/RISCV/gem5.fast -d ./HPCG_FS_results
> >> ./configs/example/gem5_library/riscv-fs.py) in order to download the
> >> riscv-bootloader-vmlinux-5.10 and riscv-disk-img.
> >> After this I mount the riscv-disk-img (sudo mount -o loop
> >> riscv-disk-img /mnt), put the xhpcg executable and I do the following
> >> changes in riscv-fs.py to boot the riscv-disk-img with executable:
> >>
> >> image = CustomDiskImageResource(
> >>  local_path = "/home/cossim/.cache/gem5/riscv-disk-img",
> >> )
> >>
> >> # Set the Full System workload.
> >> board.set_kernel_disk_workload(
> >> kernel=Resource("riscv-bootloader-vmlinux-5.10"),
> >> disk_image=image,
> >> )
> >>
> >> Finally, in the gem5/src/python/gem5/components/boards/riscv_board.py
> >> I change the last line to "return ["console=ttyS0",
> >> "root={root_value}", "rw"]" in order to allow the write permissions in
> >> the image.
> >>
> >>
> >> 2) The HPCG benchmark after some iterations calculates if the results
> >> are valid or not valid. In the case of FS it gives invalid results. As
> >> I see from the results, one (at least) problem is that produces
> >> different results in each HPCG execution (with the same configuration).
> >>
> >> Here is the HPCG output and riscv-fs.py
> >> (http://kition.mhl.tuc.gr:8000/d/68d82f3533/). You may reproduce the
> >> results in the video if you use the xhpcg executable
> >> (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/)
> >>
> >> Please help me in order to solve it!
> >>
> >> Finally, I get invalid results in the HPL benchmark in FS mode too.
> >>
> >> Best regards,
> >> Nikos
> >>
> >>
> >> Quoting Bobby Bruce :
> >>
> >> > I'm going to need a bit more information to help:
> >> >
> >> > 1. In what way have you modified
> >> > ./configs/example/gem5_library/riscv-fs.py? Can you attach the script
> >> here?
> >> > 2. What error are you getting or in what way are the results invalid?
> >> >
> >> > -
> >> > Dr. Bobby R. Bruce
> >> > Room 3050,
> >> > Kemper Hall, UC Davis
> >> > Davis,
> >> > CA, 95616
> >> >
> >> > web: https://www.bobbybruce.net
> >> >
> >> >
> >> > On Mon, Sep 19, 2022 at 1:43 PM Νικόλαος Ταμπουρατζής <
> >> > ntampourat...@ece.auth.gr> wrote:
> >> &

[gem5-users] Re: 回复:Re: 回复:Re: Different simulation results on different computers with the same configuration

2022-09-20 Thread Jason Lowe-Power
Hello,

The following two command produce very different gem5 binaries

scons build/Garnet_standalone/gem5.opt

The above command will use the Garnet_standalone "coherence" protocol. I
use quotes around coherence because that protocol is essentially an empty
protocol with no coherence. It's meant for testing networks and nothing
else.

scons build/NULL/gem5.opt

This command will use the MI_example protocol. This is a completely
different coherence protocol than Garnet_standalone. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/build_opts/NULL
for how the protocol is defined in the default build options.

You can specify the exact protocol you want when you build gem5 by using
the scons parameter `--protocol`

Cheers,
Jason

On Tue, Sep 20, 2022 at 8:08 AM 2497597 <2497...@qq.com> wrote:

> The correct result is below:
>
> average_packet_latency = 15.510408
> average_packet_latency = 15.528615
> average_packet_latency = 15.682214
> average_packet_latency = 15.695504
> average_packet_latency = 15.769957
> average_packet_latency = 15.821728
> average_packet_latency = 15.912262
> average_packet_latency = 16.051925
> average_packet_latency = 16.167249
> average_packet_latency = 16.319634
> average_packet_latency = 16.479105
> average_packet_latency = 16.725313
> average_packet_latency = 17.055812
> average_packet_latency = 17.588959
> average_packet_latency = 18.500431
> average_packet_latency = 21.669417
> average_packet_latency = 103.241365
> average_packet_latency = 273.002675
> average_packet_latency = 430.695013
> average_packet_latency = 596.634683
> average_packet_latency = 732.220679
> average_packet_latency = 854.214438
> average_packet_latency = 969.032975
> average_packet_latency = 1087.468352
> average_packet_latency = 1207.588344
>
> 1.gem5 version is v21.2.1.0
>
> 2.build command is ”scons build/NULL/gem5.opt -j 4"
>
> 3.run command is below and the "--injection-rate" is increasing with
> step=0.02
>
> Command to Run:
> ./build/NULL/gem5.opt
> configs/example/garnet_synth_traffic.py \
> --network=garnet2.0 \
> --num-cpus=64 \
> --num-dirs=64 \
> --topology=Mesh_XY \
> --mesh-rows=8 \
> --sim-cycles=1 \
> --inj-vnet=0 \
> --injectionrate=0.02 \
> --synthetic=uniform_random
>
> I find some interesting phenomenons.
> I think I figured out where the problem might be.
> It might be the permission error and the build order.
> I built "X86","ARM","NULL" on my old computer before,so I try to restore
> it all.
> Then I find the miss folder "__pycache__" come out,I think I'm going to
> get close to the root of the problem.
> But I failed.
> I rebuild a same version gem5 on my new computer with the command"”scons
> build/Garnet_standalone/gem5.opt -j 4" under the root state.
> Then I run the same script,I get the correct output.(I can see the
> average_packet_latency is increasing with the --injectionrate)
> Although I get the desired output, I can't figure out why I get the wrong
> output.
>
> -- 原始邮件 --
> *发件人:* "The gem5 Users mailing list" ;
> *发送时间:* 2022年9月20日(星期二) 晚上7:40
> *收件人:* "gem5-users";
> *主题:* [gem5-users] Re: 回复:Re: Different simulation results on different
> computers with the same configuration
>
> Not sure to understand what you mean by “correct result".
>
> Can you please provide us with:
>
>1.
>
>gem5 version (commit SHA)
>2.
>
>build command
>3.
>
>run command
>
>
> Can you please also double-check that you are using supported versions of
> python and gcc/clang. Also check that config.ini is the same in all cases.
>
> Gabriel
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>
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[gem5-users] Re: HPCG on RISCV

2022-09-20 Thread Jason Lowe-Power
Hi Nikos,

I notice you said the following in your original email:

In addition, I used the RISCV Ubuntu image
> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu),
> I installed the gcc compiler, compile it (through qemu) and I get
> wrong results too.


Is this saying you get the wrong results is QEMU? If so, the bug is in GCC
or the HPCG workload, not in gem5. If not, I would test in QEMU to make
sure the binary works there. Another way you could test to see if the
problem is your binary or gem5 would be to run it on real hardware. We have
access to some RISC-V hardware here at UC Davis, if you don't have access
to it.

Cheers,
Jason

On Tue, Sep 20, 2022 at 12:58 AM Νικόλαος Ταμπουρατζής <
ntampourat...@ece.auth.gr> wrote:

> Dear Bobby,
>
> 1) I use the original riscv-fs.py which is provided in the latest gem5
> release.
> I run the gem5 once (./build/RISCV/gem5.fast -d ./HPCG_FS_results
> ./configs/example/gem5_library/riscv-fs.py) in order to download the
> riscv-bootloader-vmlinux-5.10 and riscv-disk-img.
> After this I mount the riscv-disk-img (sudo mount -o loop
> riscv-disk-img /mnt), put the xhpcg executable and I do the following
> changes in riscv-fs.py to boot the riscv-disk-img with executable:
>
> image = CustomDiskImageResource(
>  local_path = "/home/cossim/.cache/gem5/riscv-disk-img",
> )
>
> # Set the Full System workload.
> board.set_kernel_disk_workload(
> kernel=Resource("riscv-bootloader-vmlinux-5.10"),
> disk_image=image,
> )
>
> Finally, in the gem5/src/python/gem5/components/boards/riscv_board.py
> I change the last line to "return ["console=ttyS0",
> "root={root_value}", "rw"]" in order to allow the write permissions in
> the image.
>
>
> 2) The HPCG benchmark after some iterations calculates if the results
> are valid or not valid. In the case of FS it gives invalid results. As
> I see from the results, one (at least) problem is that produces
> different results in each HPCG execution (with the same configuration).
>
> Here is the HPCG output and riscv-fs.py
> (http://kition.mhl.tuc.gr:8000/d/68d82f3533/). You may reproduce the
> results in the video if you use the xhpcg executable
> (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/)
>
> Please help me in order to solve it!
>
> Finally, I get invalid results in the HPL benchmark in FS mode too.
>
> Best regards,
> Nikos
>
>
> Quoting Bobby Bruce :
>
> > I'm going to need a bit more information to help:
> >
> > 1. In what way have you modified
> > ./configs/example/gem5_library/riscv-fs.py? Can you attach the script
> here?
> > 2. What error are you getting or in what way are the results invalid?
> >
> > -
> > Dr. Bobby R. Bruce
> > Room 3050,
> > Kemper Hall, UC Davis
> > Davis,
> > CA, 95616
> >
> > web: https://www.bobbybruce.net
> >
> >
> > On Mon, Sep 19, 2022 at 1:43 PM Νικόλαος Ταμπουρατζής <
> > ntampourat...@ece.auth.gr> wrote:
> >
> >>
> >> Dear gem5 community,
> >>
> >> I have successfully cross-compile the HPCG benchmark for RISCV (Serial
> >> version, without MPI and OpenMP). While it working properly in gem5 SE
> >> mode (./build/RISCV/gem5.fast -d ./HPCG_SE_results
> >> ./configs/example/se.py -c xhpcg --options '--nx=16 --ny=16 --nz=16
> >> --npx=1 --npy=1 --npz=1 --rt=0.1'), I get invalid results in FS
> >> simulation using "./build/RISCV/gem5.fast -d ./HPCG_FS_results
> >> ./configs/example/gem5_library/riscv-fs.py" (I mount the riscv image
> >> and put it).
> >>
> >> Can you help me please?
> >>
> >> In addition, I used the RISCV Ubuntu image
> >> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu),
> >> I installed the gcc compiler, compile it (through qemu) and I get
> >> wrong results too.
> >>
> >> Here is the Makefile which I use, the hpcg executable for RISCV
> >> (xhpcg), and a video that shows the results
> >> (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/).
> >>
> >> P.S. I use the latest gem5 version.
> >>
> >> Thank you in advance! :)
> >>
> >> Best regards,
> >> Nikos
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> >>
>
>
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[gem5-users] Re: Running Multithreaded Workload on O3CPU

2022-09-08 Thread Jason Lowe-Power
If you apply the relation chain on gerrit, it might work. See
https://gem5-review.googlesource.com/c/public/gem5/+/35836/

That relation chain has not been merged, unfortunately.

Cheers,
Jason

On Thu, Sep 8, 2022 at 1:02 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hi Prof,
>
> Thanks a lot for your response. Is there any update regarding this ticket?
> https://gem5.atlassian.net/browse/GEM5-332
>
> Correct me if I'm wrong, but I think your response implies that the
> hyperthreading is implemented by maybe not tested. If so, this is confusing
> me a bit, given the link I included above.
>
> I forgot to mention that I am using x86.
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
>
>
> On Thu, Sep 8, 2022 at 7:51 AM Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> In this case "Thread" means hardware context in the CPU (e.g., Intel
>> hyperthreads), not *core*.
>>
>> Have you configured your O3CPU to have 8 hardware contexts?
>>
>> I'll give a few short pointers:
>> 1. SPEC is single threaded (unless running SPEC rate), so there may not
>> be other software threads executing on the system
>> 2. Multithreaded cores are not tested at all in gem5. They may work, or
>> they may not.
>> 3. I have never seen anyone try to use more than two hardware contexts in
>> a core in gem5. I wouldn't be surprised if 8 hardware contexts have never
>> been tested.
>>
>> To debug this, I would probably start by having multiple CPU cores and
>> making sure things work as expected. If so, then I would try 2 threads per
>> core to see if it works, then go to 4 or 8.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Sep 8, 2022 at 2:55 AM Abdelrahman S. Hussein <
>> abdelrahman.sob...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am running a multithreaded workload on the O3 CPU in Full System Mode.
>>> The workload is SPEC OMP. I am running from a checkpoint that was taken in
>>> the middle of running the benchmark. I am using the following debugging
>>> flags to monitor the system
>>> Thread,Faults,Fetch,O3CPU
>>>
>>> However, looking at the debugging file, I always see that the fetcher
>>> only fetches from tid: 0, which means the CPU does not switch to any other
>>> Thread at all. I am sure that my workload runs on 8 threads (cooperating
>>> threads).
>>>
>>> So, does this mean that gem5 does not support running multithreaded
>>> workloads? Or, am I missing something or watching the wrong debug prints?
>>>
>>> Thanks.
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>> MSc. Student -- Graduate RA/TA
>>> School of Computing Sciences
>>> Simon Fraser University, Canada
>>> ___
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>>>
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[gem5-users] Re: Running Multithreaded Workload on O3CPU

2022-09-08 Thread Jason Lowe-Power
Hello,

In this case "Thread" means hardware context in the CPU (e.g., Intel
hyperthreads), not *core*.

Have you configured your O3CPU to have 8 hardware contexts?

I'll give a few short pointers:
1. SPEC is single threaded (unless running SPEC rate), so there may not be
other software threads executing on the system
2. Multithreaded cores are not tested at all in gem5. They may work, or
they may not.
3. I have never seen anyone try to use more than two hardware contexts in a
core in gem5. I wouldn't be surprised if 8 hardware contexts have never
been tested.

To debug this, I would probably start by having multiple CPU cores and
making sure things work as expected. If so, then I would try 2 threads per
core to see if it works, then go to 4 or 8.

Cheers,
Jason

On Thu, Sep 8, 2022 at 2:55 AM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hello,
>
> I am running a multithreaded workload on the O3 CPU in Full System Mode.
> The workload is SPEC OMP. I am running from a checkpoint that was taken in
> the middle of running the benchmark. I am using the following debugging
> flags to monitor the system
> Thread,Faults,Fetch,O3CPU
>
> However, looking at the debugging file, I always see that the fetcher only
> fetches from tid: 0, which means the CPU does not switch to any other
> Thread at all. I am sure that my workload runs on 8 threads (cooperating
> threads).
>
> So, does this mean that gem5 does not support running multithreaded
> workloads? Or, am I missing something or watching the wrong debug prints?
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
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[gem5-users] Re: Trying to add barrier to threads example

2022-09-06 Thread Jason Lowe-Power
Hi Gautam,

There are a number of limitations of SE mode including with respect to
multithreading as I described above. You may be able to get around the
functional access issue by extending the protocol to support functional
accesses better (e.g., improving the implementation of `functionalRead` and
`functionalWrite` in the cache controller). Otherwise, you can probably use
the MI_example or MESI protocols as a good example of how to implement
DMAs. Other than DMA, things *should* work in FS mode. As always, using the
Ruby random tester is faster than waiting for linux boot to run into an
error.

Cheers,
Jason

On Sat, Sep 3, 2022 at 1:10 PM Gautam Pathak 
wrote:

> Hi Prof. Jason,
>
> Thank you for the clarification. I further wanted to ask whether there is
> any other way to do multithreaded application tests correctly in SE+ruby
> mode? If not, then we'll be forced to use FS mode which afaik does not work
> currently with MSI (our modified protocol will have to be changed again
> because FS mode requires (?) DMA support). Do you have any advice for
> things to watch out for while testing our multithreaded applications in
> Full System mode?
>
> Thanks and Regards,
> Gautam Pathak
> ------
> *From:* Jason Lowe-Power 
> *Sent:* Friday, September 2, 2022 10:51 AM
> *To:* The gem5 Users mailing list 
> *Subject:* [gem5-users] Re: Trying to add barrier to threads example
>
> Hi Gautam,
>
> Functional accesses (i.e., fake/debug accesses that bypass all timing) and
> Ruby do not play well together. Fundamentally, it is hard to know what is
> the most up to date value or which value(s) you have to update when a cache
> block is in an intermediate state. With MI_example and MESI, these
> protocols probably have more support for functional reads than MSI, but
> you're also just getting lucky with those. At some point, if you're doing
> functional accesses, it's going to fail.
>
> In SE mode, to implement the fake system calls which execute *in the
> simulator* instead of via the guest kernel executing on the simulated CPU,
> we must use the fake/unrealistic/magic functional accesses. So, this is why
> SE mode + multithreading + Ruby will almost always run into a problem at
> some point. FS mode will not have this issue because it does not use
> functional accesses (almost none at all) and nothing is "faked." The
> simulated CPU executes all of the kernel system calls.
>
> Hopefully this answers your question. Let me know if I can provide more
> info :)
>
> Cheers,
> Jason
>
> On Thu, Sep 1, 2022 at 3:58 PM Gautam Pathak 
> wrote:
>
> Hi All,
>
> I'm trying to add a custom thread barrier to the array_add function by
> using __sync_fetch_and_add. The system I'm using is MSI using Ruby in SE
> mode. When I run this, I get the following error:
> build/X86/mem/ruby/system/RubyPort.cc:434: fatal: Ruby functional read
> failed for address 0x15b918.
> Till now I have observed that there is an open issue which mentions that
> Ruby+multithreading+SE is not supported. The exact fault occurs in Futex
> syscall. (Ref. https://gem5.atlassian.net/browse/GEM5-676). However, I
> have tested the same for MI_Example protocol (using simple_ruby.py) and
> MESI_Two_Level (using se.py) upto 30+ threads and it works. This makes me
> wonder whether this is an MSI protocol bug. Any suggestions on how I should
> go on about this issue would be appreciated! Otherwise, is Full System mode
> the recommended option for Ruby+custom coherence protocol+multithreading
> (possibly using atomics)?
>
> Thanks and Regards,
> Gautam Pathak
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[gem5-users] Re: Trying to add barrier to threads example

2022-09-02 Thread Jason Lowe-Power
Hi Gautam,

Functional accesses (i.e., fake/debug accesses that bypass all timing) and
Ruby do not play well together. Fundamentally, it is hard to know what is
the most up to date value or which value(s) you have to update when a cache
block is in an intermediate state. With MI_example and MESI, these
protocols probably have more support for functional reads than MSI, but
you're also just getting lucky with those. At some point, if you're doing
functional accesses, it's going to fail.

In SE mode, to implement the fake system calls which execute *in the
simulator* instead of via the guest kernel executing on the simulated CPU,
we must use the fake/unrealistic/magic functional accesses. So, this is why
SE mode + multithreading + Ruby will almost always run into a problem at
some point. FS mode will not have this issue because it does not use
functional accesses (almost none at all) and nothing is "faked." The
simulated CPU executes all of the kernel system calls.

Hopefully this answers your question. Let me know if I can provide more
info :)

Cheers,
Jason

On Thu, Sep 1, 2022 at 3:58 PM Gautam Pathak 
wrote:

> Hi All,
>
> I'm trying to add a custom thread barrier to the array_add function by
> using __sync_fetch_and_add. The system I'm using is MSI using Ruby in SE
> mode. When I run this, I get the following error:
> build/X86/mem/ruby/system/RubyPort.cc:434: fatal: Ruby functional read
> failed for address 0x15b918.
> Till now I have observed that there is an open issue which mentions that
> Ruby+multithreading+SE is not supported. The exact fault occurs in Futex
> syscall. (Ref. https://gem5.atlassian.net/browse/GEM5-676). However, I
> have tested the same for MI_Example protocol (using simple_ruby.py) and
> MESI_Two_Level (using se.py) upto 30+ threads and it works. This makes me
> wonder whether this is an MSI protocol bug. Any suggestions on how I should
> go on about this issue would be appreciated! Otherwise, is Full System mode
> the recommended option for Ruby+custom coherence protocol+multithreading
> (possibly using atomics)?
>
> Thanks and Regards,
> Gautam Pathak
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[gem5-users] Re: Is there a dev branch with 2 level TLB in X86 Full System

2022-08-31 Thread Jason Lowe-Power
Hi Arun,

There's no mainline changes which implement a two level TLB in x86. This
would be a welcome contribution, though!

Cheers,
Jason

On Wed, Aug 31, 2022 at 12:14 AM Arun Kavumkal 
wrote:

> Hi All,
> I would like to know whether there is any ongoing work to implement 2
> level TLB in X86 FS. I understand that ARM has 2 level TLB implementation.
> I was wondering if there is an ongoing development activity for 2 level
> TLB in X86, I can use that for the time being
>
> Thanks
> Arun KP
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[gem5-users] Re: Linux not booting on x86 (timing cpu, single core) after pulling latest stable branch

2022-08-08 Thread Jason Lowe-Power
Hi Arun,

Can you give us some details on the error that you're experiencing?

Thanks,
Jason

On Sun, Aug 7, 2022 at 7:48 AM Arun Kavumkal 
wrote:

> Dear All,
> I was able to boot Linux v5.2.3 on x86 system (timing cpu, single core)
> and execute benchmarks using gem5art (https://github.com/darchr/gem5art),
> but after pulling latest changes in stable branch (till Commits on Jul 29,
> 2022), I am not able to boot linux using gem5art.
>
> Arun KP
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[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

2022-07-28 Thread Jason Lowe-Power
Hello,

No, I would not count on all of the instructions being fully implemented.
However, every time gem5 encounters an unimplemented instruction it will
print a warning. You can use those warnings to decide if the unimplemented
instructions are important for your workload or not.

Cheers,
Jason

On Wed, Jul 27, 2022 at 5:02 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hi,
>
> Thanks a lot for your reply.
>
> I got the CPU info by printing the /proc/cpuinfo file on the image while
> on full system mode on gem5. Can we safely assume that the following flags
> are fully implemented and functional? For example, as per this page from
> gem5 documentation
> <https://www.gem5.org/documentation/general_docs/architecture_support/>,
> only SSE is implemented and x87 is partially implemented, however, the
> following flags say something a bit different that SSE2 is supported.
>
> So, again, my question is: Can I safely rely on these flags being fully
> implemented?
>
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat
>> pse36 clflush acpi mmx fxsr sse sse2 ss tm ia64 pbe syscall nx mmxext
>> fxsr_opt rdtscp lm 3dnowext 3dnow nopl cpuid pni monitor ssse3 lahf_lm cpb
>> proc_feedback pti clflushopt clwb overflow_recov
>
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
>
>
> On Tue, Jul 26, 2022 at 7:53 AM Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> We support some of those instructions, but not all of them. I suggest
>> running your workloads and watching out for unimplemented instruction
>> warnings.
>>
>> Cheers,
>> Jason
>>
>> On Mon, Jul 25, 2022 at 11:08 PM Abdelrahman S. Hussein <
>> abdelrahman.sob...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am trying to run SPEC OMP 2012 in Full System mode on gem5. When I try
>>> to run it, I get the following error:
>>>
>>> Please verify that both the operating system and the processor support
>>>> Intel(R) X87, CMOV, MMX, FXSAVE, SSE, SSE2, SSE3, SSSE3, SSE4_1, SSE4_2 and
>>>> POPCNT instructions.
>>>>
>>>
>>> The image has Ubuntu 18 and the kernel is vmlinux-5.4.49 downloaded
>>> from gem5 website. CPU is AtomicCPU and all the implementation is for x86.
>>>
>>> My question is: does gem5 support the above Intel extensions  for SIMD
>>> and Vectorization? I tried to look into the gem5 resources, but I couldn't
>>> find something clear on this.
>>>
>>> Thanks!
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>> MSc. Student -- Graduate RA/TA
>>> School of Computing Sciences
>>> Simon Fraser University, Canada
>>> --
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>> MSc. Student -- Graduate RA/TA
>>> School of Computing Sciences
>>> Simon Fraser University, Canada
>>> ___
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[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

2022-07-26 Thread Jason Lowe-Power
Hello,

We support some of those instructions, but not all of them. I suggest
running your workloads and watching out for unimplemented instruction
warnings.

Cheers,
Jason

On Mon, Jul 25, 2022 at 11:08 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hello,
>
> I am trying to run SPEC OMP 2012 in Full System mode on gem5. When I try
> to run it, I get the following error:
>
> Please verify that both the operating system and the processor support
>> Intel(R) X87, CMOV, MMX, FXSAVE, SSE, SSE2, SSE3, SSSE3, SSE4_1, SSE4_2 and
>> POPCNT instructions.
>>
>
> The image has Ubuntu 18 and the kernel is vmlinux-5.4.49 downloaded from
> gem5 website. CPU is AtomicCPU and all the implementation is for x86.
>
> My question is: does gem5 support the above Intel extensions  for SIMD and
> Vectorization? I tried to look into the gem5 resources, but I couldn't find
> something clear on this.
>
> Thanks!
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
> --
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
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[gem5-users] Re: Running gem5 with DRAMsim3

2022-07-25 Thread Jason Lowe-Power
Hello,

We can only support the official gem5 repository found at
https://gem5.googlesource.com/. You can find the information on how to use
DRAMSim3 in the README
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/ext/dramsim3/README

Cheers,
Jason

On Sat, Jul 23, 2022 at 9:49 AM Thomas Copper 
wrote:

> Hi, Mahyar, what if I am using gem5 version in this url:
> https://github.com/umd-memsys/gem5 ?
> How can I integrate dramsim3 and gem5 together?
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[gem5-users] Re: turn off gem5 mailing list

2022-07-07 Thread Jason Lowe-Power
Hello,

At the end of all messages it says "To unsubscribe send an email to
gem5-users-le...@gem5.org"

You can also manage your subscription at
https://harmonylists.io/list/gem5-users.gem5.org by creating an account and
logging in.

Cheers,
Jason

On Thu, Jul 7, 2022 at 7:14 AM Zhipeng Cao  wrote:

>
> How can I turn off gem5 mailing list?
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[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

2022-07-06 Thread Jason Lowe-Power
Hi Zehan,

I wouldn't say it converts the timing request to atomic. Instead, I would
say that for the *functional access* (sorry for the overloaded term here...
I mean functional as in the place it does the "execution" part of the
model) it uses the same C++ function for both timing and atomic. The timing
should be handled in the delay when the sendTimingReq or sendTimingResp
events are scheduled.

Cheers,
Jason

On Wed, Jul 6, 2022 at 8:21 AM Zehan Gao  wrote:

> Thanks for your advice. My guess is that it's the ports connected to the
> atomic-only port converts a timing request to atomic, and calls the
> recvAtomic function. In this case it's the XBar. I will try to measure how
> it's delayed.
>
> ------
> *From:* Jason Lowe-Power 
> *Sent:* Wednesday, July 6, 2022, 11:09 a.m.
> *To:* The gem5 Users mailing list 
> *Subject:* [gem5-users] Re: What happens when a atomic only port is
> accessed in Timing simulation?
>
> Hi Zehan,
>
> Atomic memory accesses should not be used during the same simulation loop
> as timing accesses. I.e., you should not call "sendAtomic" on a port during
> the same simulation loop that you call "sendTiming". If there isn't a panic
> in that case, there probably should be.
>
> If you want to get a value out of memory in 0 time (e.g., for debugging or
> to model a "perfect" hardware component) you can use *functional* accesses
> during the timing simulation. You can also exit the simulation loop and
> switch between timing and atomic modes.
>
> Cheers,
> Jason
>
> On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao  wrote:
>
>> Hi All,
>>
>>   I am building a simulated system with a control registers
>> port that only implemented recvAtomic function. The control port is
>> connected to the IOBridge, and the system is running in timing mode. There
>> is no problem to access the registers from CPU, but I wonder what the
>> system does with the delay? I believe the atomic port would be treated as a
>> timing port that has no delays. But is the delay of IOBridge and other
>> system buses counted?
>>
>>
>>
>> Thanks,
>>
>> Zehan
>>
>>
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[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

2022-07-06 Thread Jason Lowe-Power
Hi Zehan,

Atomic memory accesses should not be used during the same simulation loop
as timing accesses. I.e., you should not call "sendAtomic" on a port during
the same simulation loop that you call "sendTiming". If there isn't a panic
in that case, there probably should be.

If you want to get a value out of memory in 0 time (e.g., for debugging or
to model a "perfect" hardware component) you can use *functional* accesses
during the timing simulation. You can also exit the simulation loop and
switch between timing and atomic modes.

Cheers,
Jason

On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao  wrote:

> Hi All,
>
>   I am building a simulated system with a control registers
> port that only implemented recvAtomic function. The control port is
> connected to the IOBridge, and the system is running in timing mode. There
> is no problem to access the registers from CPU, but I wonder what the
> system does with the delay? I believe the atomic port would be treated as a
> timing port that has no delays. But is the delay of IOBridge and other
> system buses counted?
>
>
>
> Thanks,
>
> Zehan
>
>
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[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

2022-06-27 Thread Jason Lowe-Power
Hi Syam,

In a much older version of gem5, maybe. It's been at least 2+ years since
we required the PID to be specified in SE mode.

Cheers,
Jason

On Mon, Jun 27, 2022 at 5:37 AM Syam Sankar  wrote:

> Dear Dr. Jason
>
> Thank you for your kind reply.
> I think this worked fine with the older version of gem5, right?
>
> Regards
> Syam
>
> On Fri, 24 Jun 2022, 12:43 am Jason Lowe-Power, 
> wrote:
>
>> Hi Syam,
>>
>> The error is that in *SE mode* you have to manually specify the PID for
>> each process when you are creating the processes in Python. However, I
>> think you're going to run into many problems trying to simulate such a
>> large system/workload in SE mode. For instance, I seriously doubt 3GB is
>> enough RAM for 64 copies of namd.
>>
>> We are working towards deprecating se/fs.py because they do not support
>> the flexibility required for different kinds of simulations. I would
>> suggest looking into extending the standard library with a new board to
>> model your system. Right now, we don't have any prebuilt boards at this
>> scale, but adding one is relatively straightforward. You can find
>> documentation on the standard library on the website, in our recent ISCA
>> tutorial (see our youtube channel), and we'll have more in a couple of
>> weeks.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Jun 23, 2022 at 9:01 AM Syam Sankar 
>> wrote:
>>
>>> Hi all
>>>
>>>
>>> I downloaded a new version of gem5 repo*(gem5 version 22.0.0.1)*
>>> I could build it with the following command:
>>>
>>> *python3 `which scons` build/X86/gem5.fast RUBY=true
>>> PROTOCOL=MESI_Two_Level  -j 8*
>>>
>>> I was trying to execute a *CPU2017 Benchmark* program on an 8X8 Core
>>> system with the command as follows:
>>>
>>>
>>> build/X86/gem5.fast configs/example/se.py  --num-cpus=64 --num-dirs=64
>>>  --sys-clock=2GHz --topology=Mesh_XY --mesh-rows=8 --ruby --num-l2caches=64
>>> --network=garnet   --caches --mem-type=DDR3_1600_8x8 --mem-size=3GB
>>>  --routing-algorithm=1 -F 1000 -W 1000 -I 5000
>>> --bench=namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd
>>>
>>>
>>>  But, the execution is ended with an error:
>>>
>>>
>>> *build/X86/sim/process.cc:141: fatal: fatal condition !ret_pair.second
>>> occurred: _pid 100 is already used*
>>>
>>> ...
>>> ..
>>> ..
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the ad

[gem5-users] Re: O3CPU "panic: Is stalled should have been cleared by stalling load!" when simulating for >5Billion insts, SE and FS, AARCH64

2022-06-23 Thread Jason Lowe-Power
Hi Norbert,

This is going to be a tough bug to track down! I would suggest enabling the
Exec debug flag (and maybe some others for the O3CPU) and using
--debug-start and starting the debug dumping a billion ticks or so before
the error happens. Hopefully, you can then trace back what is causing the
error. My bet is that there is some specific sequence of instructions which
is causing this.

This isn't an error I've seen before, so it's going to take some digging :).

Cheers,
Jason

On Thu, Jun 23, 2022 at 5:52 AM Norbertas Kremeris <
norbertas.kreme...@huawei.com> wrote:

> Hello all,
>
>
>
> I’m looking for some help regarding failing simulations. My host system is
> running Ubuntu 20.04 x86, and the gem5 source version is v21.2.1.1
>
>
>
> I have started running long simulations, and ran into a problem with the
> O3CPU model. I seem to have no issues running up to around 5 Billion
> instructions, some binaries up to 10 Billion, but not a single binary up to
> 20Billion, because the O3CPU model terminates the gem5 simulations with the
> following error:
>
>
>
> build/ARM/cpu/o3/lsq_unit.cc:1018: panic: Is stalled should have been
> cleared by stalling load!
>
>
>
> This happens both in full system and in syscall emulation. I am using
> aarch64. This does not happen with atomic or timing cpu variants.
>
>
>
> I am trying to run a select number of spec2017 benchmarks, namely
>
> 507.cactuBSSN_r, 607.cactuBSSN_s, 638.imagick_s, 500.perlbench_r_param3,
> 502.gcc_r_param4, 641.leela_s
>
>
>
> Out of all of the above benchmarks, all successfully run up to 5B, image
> magic is the only one that runs up to 10B, and none of them run up to 20B
> instructions, and this is the same case for both FS and SE simulations.
>
>
>
> The O3 model code in question is in src/cpu/o3/lsq_unit.cc, but I don’t
> know enough to try and debug this issue:
>
>
>
> 1014 // I don't think this can happen.  It should have been cleared
>
> 1015 // by the stalling load.
>
> 1016 if (isStalled() &&
>
> 1017 storeQueue.back().instruction()->seqNum ==
> stallingStoreIsn) {
>
> 1018 panic("Is stalled should have been cleared by stalling
> load!\n");
>
> 1019 stalled = false;
>
> 1020 stallingStoreIsn = 0;
>
> 1021 }
>
>
>
> Below are the details of some example simulation runs that fail, alongside
> the full stderr output.
>
>
>
> Aarch64 Full System (restoring from checkpoint made with atomic cpu):
>
> Config: configs/example/fs.py
>
> System args:
>
>--mem-size="8000MB" \
>
> --cpu-type="O3CPU" \
>
> --restore-with-cpu="O3CPU" \
>
> --caches \
>
> --l2cache \
>
> -I="100" \
>
>
>
> Error:
>
> build/ARM/cpu/o3/lsq_unit.cc:1018: panic: Is stalled should have been
> cleared by stalling load!
>
> Memory Usage: 8979848 KBytes
>
> Program aborted at tick 5929446216500
>
> --- BEGIN LIBC BACKTRACE ---
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1a94570)[0x55a0cd625570]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1aa8f4e)[0x55a0cd639f4e]
>
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x143c0)[0x7f70b6d913c0]
>
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xcb)[0x7f70b5f3703b]
>
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x12b)[0x7f70b5f16859]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x576a35)[0x55a0cc107a35]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb2c153)[0x55a0cc6bd153]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb0dd36)[0x55a0cc69ed36]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb0eaa3)[0x55a0cc69faa3]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb0ffbe)[0x55a0cc6a0fbe]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xaedc7f)[0x55a0cc67ec7f]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1a9ca68)[0x55a0cd62da68]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1abf564)[0x55a0cd650564]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1ac022e)[0x55a0cd65122e]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb92c22)[0x55a0cc723c22]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xa6a1cd)[0x55a0cc5fb1cd]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x2a8738)[0x7f70b7048738]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x8dd8)[0x7f70b6e1df48]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7f70b6f6ae3b]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyFunction_Vectorcall+0x94)[0x7f70b7048114]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f70b6e14d6d]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7f70b6e1cef6]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x8006b)[0x7f70b6e2006b]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f70b6e14d6d]
>
>
> 

[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

2022-06-23 Thread Jason Lowe-Power
Hi Syam,

The error is that in *SE mode* you have to manually specify the PID for
each process when you are creating the processes in Python. However, I
think you're going to run into many problems trying to simulate such a
large system/workload in SE mode. For instance, I seriously doubt 3GB is
enough RAM for 64 copies of namd.

We are working towards deprecating se/fs.py because they do not support the
flexibility required for different kinds of simulations. I would suggest
looking into extending the standard library with a new board to model your
system. Right now, we don't have any prebuilt boards at this scale, but
adding one is relatively straightforward. You can find documentation on the
standard library on the website, in our recent ISCA tutorial (see our
youtube channel), and we'll have more in a couple of weeks.

Cheers,
Jason

On Thu, Jun 23, 2022 at 9:01 AM Syam Sankar  wrote:

> Hi all
>
>
> I downloaded a new version of gem5 repo*(gem5 version 22.0.0.1)*
> I could build it with the following command:
>
> *python3 `which scons` build/X86/gem5.fast RUBY=true
> PROTOCOL=MESI_Two_Level  -j 8*
>
> I was trying to execute a *CPU2017 Benchmark* program on an 8X8 Core
> system with the command as follows:
>
>
> build/X86/gem5.fast configs/example/se.py  --num-cpus=64 --num-dirs=64
>  --sys-clock=2GHz --topology=Mesh_XY --mesh-rows=8 --ruby --num-l2caches=64
> --network=garnet   --caches --mem-type=DDR3_1600_8x8 --mem-size=3GB
>  --routing-algorithm=1 -F 1000 -W 1000 -I 5000
> --bench=namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd
>
>
>  But, the execution is ended with an error:
>
>
> *build/X86/sim/process.cc:141: fatal: fatal condition !ret_pair.second
> occurred: _pid 100 is already used*
>
> ...
> ..
> ..
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned 

[gem5-users] Re: Gem5 segfaults in build/X86/cpu/o3/fetch.cc

2022-06-13 Thread Jason Lowe-Power
Hi Gagan,

The problem is that the CPU doesn't have an ISA object as a child. Most
likely, the function `createThreads()` wasn't called on the CPU instance.
You need to set all of this up *in the python configuration*, not in the
C++ models.

Solving this problem is difficult if you're using the (soon to be)
deprecated fs.py script. This script tries to do everything for everyone
and ends up doing nothing well. I suggest looking into the new gem5
standard library and working to create a board which suits your needs. See
https://www.gem5.org/documentation/gem5-stdlib/overview

Cheers,
Jason

On Sun, Jun 12, 2022 at 11:11 PM Gagan Panwar  wrote:

> Hi everyone,
>
> I'm trying to run the latest version of Gem5 under X86 and it segfaults at
> the following line:
>
> build/X86/cpu/o3/fetch.cc:139
> > decoder[tid] = params.decoder[tid];
>
> gdb says params.decoder is a "vector of length 0". Looks like it has not
> been initialized.
>
> Any idea how to correctly initialize this?
>
> Here is my command line:
>
> ./build/X86/gem5.opt -r -d sim_output/stride/benchmark
> configs/example/fs.py --mem-size=16GB -n 4 -r 1
> --disk-image=/hdd0/newCPTs/ubuntu-server-16.04.6.img --checkpoint-dir=
> /hdd0/newCPTs/bench_1 --cpu-type=DerivO3CPU --rel-max-tick=20
> --l2-hwp-type=StridePrefetcher --caches --l2cache --kernel=vmlinux-5.4.49
>
> I have also tried assigning decoder[tid] to a new TheISA::Decoder() object
> in fetch.cc like it used to be in older versions but this leads to build
> issues.
>
> To reiterate, I have not modified a single line of code. I was able to
> take checkpoints under KVM mode successfully, however.
>
> Thank you,
> Gagan
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>
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[gem5-users] Re: "No alive nodes found in your cluster"

2022-06-06 Thread Jason Lowe-Power
Hi Jason,

To be honest, the mailman server isn't great at providing search/archiving.
I would search on mail-archive (link in previous email below) and/or use
google :).

Cheers,
Jason

On Mon, Jun 6, 2022 at 4:48 PM  wrote:

> Hi Jason,
>
>
> Thank you for your reply, I am using the “Search this list” box on the
> harmonylists.io website that says “EMPATHY” at the top left:
> https://harmonylists.io/empathy/list/gem5-users.gem5.org
>
>
> Is this the correct website to search? I allowed me to post a new thread
> question from here, but when I try to search it, it gives me the error
> described earlier. I had trouble finding where to look after the change to
> the new website, so I’m not sure if I’m using the correct one or not.
>
>
> Thank you for your time!
>
>
> Respectfully,
>
>
> Jason Z.
>
>
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>
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[gem5-users] Re: "No alive nodes found in your cluster"

2022-06-06 Thread Jason Lowe-Power
Hi Jason,

I'm not sure where you were trying to search. However, mail archive (
https://www.mail-archive.com/gem5-users@gem5.org/) is usually pretty
reliable. If that's not working for you, you may be able to reach out to
their support.

Cheers,
Jason

On Mon, Jun 6, 2022 at 4:13 PM  wrote:

> Hi everyone,
>
>
> I was trying to search the gem5-users discussion forum for a question I
> had to see if it was already addressed, but it keeps giving me an error
> with “No alive nodes found in your cluster” and says
> “NoNodesAvailableException”, so is this an issue with the discussion forum?
>
>
> Thank you for your time!
>
>
> Respectfully,
>
>
> Jason Z.
>
>
>
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: mail sent to mailing list not visible in gem5-users Mail archive

2022-05-31 Thread Jason Lowe-Power
Hi Javed,

I received that message. No idea why it doesn't show up on mail archive..

Cheers,
Jason

On Tue, May 31, 2022 at 3:33 AM Javed Osmany 
wrote:

> Hello
>
>
>
> I sent an email the gem5-users mailing list on the 27th May 2022, titled
> “CHI compilation error when trying to add L3$ between L2$ and LLC”, but I
> don’t see that email listed in the gem5-users Mail archive (
> https://www.mail-archive.com/gem5-users@gem5.org/index.html).
>
>
>
> Am I posting to the wrong email or has it just got lost?
>
>
>
> Tks
>
> JO
>
>
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: How to make _addr version of m5 ops work on x86+syscall emulation?

2022-05-12 Thread Jason Lowe-Power
Hello,

In the first case, since you're using SE mode, gem5 is trying to use
/dev/mem *on your host*, not on the guest. The addr interface for the m5
ops is really meant for FS mode, not SE mode.

In the second case, this is probably because KVM + SE mode is rarely, if
ever, tested. I'm not surprised there's a bug, though you could try the
most recent release of gem5, 21.2.

Cheers,
Jason

On Thu, May 12, 2022 at 7:26 AM  wrote:

> Hi all,
>
> I'm trying to run *_addr* *m5ops*. I need the _addr version because I
> want to implement a pseudo instruction that works in all gem5 cpu types,
> including KVM, which only supports _addr pseudo instructions.
>
> If I use this code (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2/src/simple/m5_exit_addr.c
> )
>
> as example:
>
> #include 
> #include 
> #include 
> int main(void) {
> #if defined(__aarch64__)
> m5op_addr = 0x1001;
> #endif
> map_m5_mem();
> m5_exit_addr(0);
> }
>
> I built m5ops following
> https://www.gem5.org/documentation/general_docs/m5ops/
>
> I compile the test application with:
>
> gcc test.c -o test -L ~/Projects/gem5/util/m5/build/x86/out -lm5 -I
> ~/Projects/gem5/include -I ~/Projects/gem5/util/m5/src -static
>
> If I run with AtomicSimpleCPU I get
>
> ./build/X86/gem5.opt configs/example/se.py -c
> tests/test-progs/pedro-test/test --cpu-type AtomicSimpleCPU
>
>  REAL SIMULATION 
> build/X86/sim/simulate.cc:107: info: Entering event queue @ 0. Starting
> simulation...
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> build/X86/sim/syscall_emul.cc:73: warn: ignoring syscall mprotect(...)
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> Can't open /dev/mem: Permission denied
> Exiting @ tick 11031000 because exiting with last active thread context
> Simulated exit code not 0! Exit code is 1
>
> If I run with KvmCPU
>
> ./build/X86/gem5.opt configs/example/se.py -c
> tests/test-progs/pedro-test/test --cpu-type X86KvmCPU
>
> [...]
>
> build/X86/cpu/kvm/x86_cpu.cc:1556: warn: kvm-x86: MSR (0x491) unsupported
> by gem5. Skipping.
> build/X86/cpu/kvm/x86_cpu.cc:1556: warn: kvm-x86: MSR (0xc0010015)
> unsupported by gem5. Skipping.
> build/X86/cpu/kvm/x86_cpu.cc:1556: warn: kvm-x86: MSR (0x4b564d05)
> unsupported by gem5. Skipping.
> build/X86/cpu/kvm/x86_cpu.cc:450: warn: Illegal SS type: 1
> build/X86/cpu/kvm/x86_cpu.cc:491: warn: ss: S flag not set
> build/X86/cpu/kvm/x86_cpu.cc:517: warn: ss: P flag not set
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> build/X86/cpu/kvm/x86_cpu.cc:450: warn: Illegal SS type: 1
> build/X86/cpu/kvm/x86_cpu.cc:491: warn: ss: S flag not set
> build/X86/cpu/kvm/x86_cpu.cc:517: warn: ss: P flag not set
> build/X86/cpu/kvm/x86_cpu.cc:450: warn: Illegal SS type: 1
> build/X86/cpu/kvm/x86_cpu.cc:491: warn: ss: S flag not set
> build/X86/cpu/kvm/x86_cpu.cc:517: warn: ss: P flag not set
> build/X86/sim/syscall_emul.cc:73: warn: ignoring syscall mprotect(...)
> build/X86/arch/x86/linux/se_workload.cc:162: panic: Page fault at addr 0
> Interrupt handler stack:
> ss: 0x1b
> rsp: 0x7fffed18
> rflags: 0x10006
> cs: 0x23
> rip: 0x45ca46
> err_code: 0x4
> Memory Usage: 636056 KBytes
> Program aborted at tick 441533000
> --- BEGIN LIBC BACKTRACE ---
> ./build/X86/gem5.opt(+0x883420)[0x560e0d238420]
> ./build/X86/gem5.opt(+0x8a4ade)[0x560e0d259ade]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x143c0)[0x7f7c671cb3c0]
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xcb)[0x7f7c6637103b]
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x12b)[0x7f7c66350859]
> ./build/X86/gem5.opt(+0x30b5e5)[0x560e0ccc05e5]
> ./build/X86/gem5.opt(+0xd6109c)[0x560e0d71609c]
> ./build/X86/gem5.opt(+0xd611db)[0x560e0d7161db]
> ./build/X86/gem5.opt(+0x913645)[0x560e0d2c8645]
> ./build/X86/gem5.opt(+0x9827ee)[0x560e0d3377ee]
> ./build/X86/gem5.opt(+0x983a1a)[0x560e0d338a1a]
> ./build/X86/gem5.opt(+0x9811c1)[0x560e0d3361c1]
> ./build/X86/gem5.opt(+0x552ba6)[0x560e0cf07ba6]
> ./build/X86/gem5.opt(+0x5530ae)[0x560e0cf080ae]
> ./build/X86/gem5.opt(+0x551b91)[0x560e0cf06b91]
> ./build/X86/gem5.opt(+0x892796)[0x560e0d247796]
> ./build/X86/gem5.opt(+0x8c14f4)[0x560e0d2764f4]
> ./build/X86/gem5.opt(+0x8c1d42)[0x560e0d276d42]
> ./build/X86/gem5.opt(+0xe1ec92)[0x560e0d7d3c92]
> ./build/X86/gem5.opt(+0x5bfef1)[0x560e0cf74ef1]
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x2a8738)[0x7f7c67482738]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x8dd8)[0x7f7c67257f48]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7f7c673a4e3b]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyFunction_Vectorcall+0x94)[0x7f7c67482114]
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f7c6724ed6d]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7f7c67256ef6]
> 

[gem5-users] Re: virtual address -> base + offset

2022-05-09 Thread Jason Lowe-Power
Hi Sindhuja,

I'm not sure exactly what you're looking for when you say "base and
offset." I believe you can query the base page size from the ISA (I forget
the exact function). With that you can divide and use modulo to compute the
VPN/PPN and the offset. You can also look at the TLB code to see how it
computes these things.

Cheers,
Jason

On Mon, May 9, 2022 at 2:54 PM Sindhuja Gopalakrishnan Elango <
sindhuja.gopalakrishnanela...@synopsys.com> wrote:

> Hi Jason,
>
> Thanks for the reply.
>
> I had managed to get both physical address and virtual address of the
> memory address through the request
>
> object like this.
>
> req->getPaddr();
>
> req->getVaddr();
>
> But I would like to extract the base and offset component of the virtual
> address as separate entities. Is that also possible?
>
>
>
> Thanks,
>
> Sindhuja
>
>
>
> *From:* Jason Lowe-Power 
> *Sent:* Monday, May 9, 2022 1:34 PM
> *To:* The gem5 Users mailing list 
> *Subject:* [gem5-users] Re: virtual address -> base + offset
>
>
>
> Hi Sindhuja,
>
>
>
> The WholeTranslationState object should have all of the virtual and
> physical address information. In fact, the Request object (a member of the
> Packet) should also have both virtual and physical addresses.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Mon, May 9, 2022 at 10:23 AM Sindhuja Gopalakrishnan Elango <
> sindhuja.gopalakrishnanela...@synopsys.com> wrote:
>
> Hi,
>
> Is it possible to get the base and offset components of the virtual memory
> address in the CPU model?
>
> Appreciate your comments.
>
>
>
> Thanks,
>
> Sindhuja
>
>
>
>
>
>
>
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>
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[gem5-users] Re: virtual address -> base + offset

2022-05-09 Thread Jason Lowe-Power
Hi Sindhuja,

The WholeTranslationState object should have all of the virtual and
physical address information. In fact, the Request object (a member of the
Packet) should also have both virtual and physical addresses.

Cheers,
Jason

On Mon, May 9, 2022 at 10:23 AM Sindhuja Gopalakrishnan Elango <
sindhuja.gopalakrishnanela...@synopsys.com> wrote:

> Hi,
>
> Is it possible to get the base and offset components of the virtual memory
> address in the CPU model?
>
> Appreciate your comments.
>
>
>
> Thanks,
>
> Sindhuja
>
>
>
>
>
>
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>
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[gem5-users] Re: fatal: Syscall 278 out of range (ARM) - can i skip/supress syscall unimplemeted errors

2022-05-09 Thread Jason Lowe-Power
Hi Tom,

My guess is that you're using a newer version of GLIBC which calles
different syscalls than the versions of GLIBC that have been tested with
gem5. I believe 278 is mq_notify. You can try to update the syscall
implementation to ignore the syscall and see if the application still
works. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/arm/linux/se_workload.cc#404

Another possibility is that you're using a 32-bit emulated process with a
64-bit binary, or something has gone wrong with whether it's detected as
Arm32 or Arm64. In the 64-bit version, 278 is getRandom, which is
implemented. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/arm/linux/se_workload.cc#762

Hope this helps!

Cheers,
Jason

On Fri, May 6, 2022 at 6:33 PM  wrote:

> Hi All,
>
> I am trying to run dhrystone benchmark on ARM and i get the following:
>
> ./build/ARM/gem5.opt --debug-flags=Exec
> --debug-file=dhrystone_10k_a77_trace ./configs/example/arm/starter_se.py
> --cpu minor --cpu-freq 3.0GHz --mem-type DDR4_2400_8x8
> ./tests/dhrystone_10k
>
> gem5 Simulator System. http://gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.2.1.0
>
> gem5 compiled Apr 27 2022 18:13:35
>
> gem5 started May 7 2022 01:55:59
>
> gem5 executing on eden, pid 4723
>
> command line: ./build/ARM/gem5.opt --debug-flags=Exec
> --debug-file=dhrystone_10k_a77_trace ./configs/example/arm/starter_se.py
> --cpu minor --cpu-freq 3.0GHz --mem-type DDR4_2400_8x8 ./tests/dhrystone_10k
>
> info: 1. command and arguments: ['./tests/dhrystone_10k']
>
> Global frequency set at 1 ticks per second
>
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
>
> build/ARM/mem/mem_interface.cc:791: warn: DRAM device capacity (16384
> Mbytes) does not match the address range assigned (1024 Mbytes)
>
> build/ARM/mem/mem_interface.cc:791: warn: DRAM device capacity (16384
> Mbytes) does not match the address range assigned (1024 Mbytes)
>
> build/ARM/base/statistics.hh:280: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
>
> build/ARM/base/statistics.hh:280: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
> build/ARM/sim/simulate.cc:194: info: Entering event queue @ 0. Starting
> simulation...
>
> build/ARM/sim/syscall_emul.cc:74: warn: ignoring syscall
> set_robust_list(...)
>
> build/ARM/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/ARM/sim/syscall_emul.hh:1014: warn: readlink() called on
> '/proc/self/exe' may yield unexpected results in various settings.
>
> Returning '/home/tom/Documents/gem5/tests/dhrystone_10k'
>
> build/ARM/sim/syscall_desc.hh:209: fatal: Syscall 278 out of range
>
> Memory Usage: 2237648 KBytes
>
>
> This is my new install on a new machine. In my older machine, i had run
> the dhrystone for loop count of 1 million without any error. The new
> install uses the latest stable patch.
>
> Any help is appreciated.
>
> Regards,
>
> Tom
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[gem5-users] Re: Adding DmaDevice leads to TypeError: No constructor defined

2022-04-28 Thread Jason Lowe-Power
Hello,

The `DMADevice` is also abstract. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/dev/Device.py#82

Maybe what you're trying to do would be best accomplished by adding a new
SimObject which inherits from DMADevice.

Cheers,
Jason

On Wed, Apr 27, 2022 at 9:45 AM  wrote:

> Jason,
>
>
>
> Thanks for again for the fix related to PioDevice & your guidance to use
> DmaDevice
>
>
>
> DmaDevice also provides same “No Constructor TypeError” which checking the
> dma_device.cc – the constructor is empty
>
>
>
>
>
>
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
> exec (filecode, scope)
>   File "/home/raghu/gem5/configs/learning_gem5/part1/test.py", line 187,
> in 
> m5.instantiate()
>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
> for obj in root.descendants(): obj.createCCObject()
>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
> self.getCCParams()
>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
> cc_params = cc_params_struct()
>
> TypeError: _m5.param_DmaDevice.DmaDeviceParams: No constructor defined!
>
>
>
> *Dma_device.cc*
>
> DmaDevice::DmaDevice(const Params )
>
>  : PioDevice(p), dmaPort(this, sys, p.sid, p.ssid)
>
> { }
>
>
>
> *From:* Jason Lowe-Power via gem5-users 
> *Sent:* Friday, April 22, 2022 11:16 AM
> *To:* gem5 users mailing list 
> *Cc:* rshank...@austin.rr.com; Jason Lowe-Power 
> *Subject:* [gem5-users] Re: Adding PioDevice leads to TypeError: No
> constructor defined
>
>
>
> I just pushed a change that will make this error message better.
>
>
>
> "fatal: Cannot instantiate an abstract SimObject (system.dev)" is what
> the error now says :).
>
>
>
> See https://gem5-review.googlesource.com/c/public/gem5/+/59049
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Power 
> wrote:
>
> Hello,
>
>
>
> I believe the problem is that gem5 tries to do too much automatically for
> you! gem5 automatically creates a lot of the constructor/destructor codes.
> Given all of this hidden/automatic code generation, it's difficult to know
> exactly what's going wrong (for both you and for us).
>
>
>
> That said, I think the problem is that `PioDevice` is an abstract
> SimObject, not a concrete SimObject. This may work if you instead use the
> `DmaDevice`.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
> gem5-users@gem5.org> wrote:
>
> By adding a PioDevice() to my version of two_level.py configuration
> script, I get this error
>
>
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
> And checking io_device.cc the constructor looks empty
>
>
>
> Any help please? Thanks
>
>
>
> *Details:*
>
>
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
> exec(filecode, scope)
>
>
>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
> 187, in 
> m5.instantiate()
>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>
>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
> self.getCCParams()
>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
> cc_params = cc_params_struct()
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
>
>
>
>
> *Io_device.cc*
>
> include "dev/io_device.hh"
>
> #include "base/trace.hh"
> #include "debug/AddrRanges.hh"
> #include "sim/system.hh"
>
> namespace gem5
> {
>
> PioDevice::PioDevice(const Params )
> : ClockedObject(p), sys(p.system), pioPort(this)
> {}
>
> PioDevice::~PioDevice()
> {
> }
>
>
>
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> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
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[gem5-users] Test email please ignore

2022-04-26 Thread Jason Lowe-Power
Sorry for the spam.

We're working to fix the issues that some people have been having with our
mailing list. I hope this will be the last test email for a while!

Cheers,
Jason
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[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

2022-04-23 Thread Jason Lowe-Power via gem5-users
Majid,

These are all great suggestions! Do you have a configuration file that you
would be willing to share? It would be a huge benefit to the community if
we had some better default configurations in the "examples" for gem5
configuration files.

We're also trying to use the new standard library for these kinds of "good"
configurations. We can work with you to create a "prebuilt board" with all
of these parameters and even run nightly/weekly tests to make sure there
are no performance regressions.

Thanks!
Jason

On Fri, Apr 22, 2022 at 7:52 PM Majid Jalili  wrote:

> I think it is hard to get to a real machine level in terms of BW. But By
> looking at your stats, I found the lsqFullEvents is high.
> You can go after the CPU to make it more aggressive, increasing Load/Store
> queue size, and ROB depth are the minimal changes you can make. I
> usually do at least ROB sizes of 256 or 320. With that, you may set the LSQ
> size to at least 1/4  of ROB size.
> For MSHRs, your numbers are good now, 10 is too little even in intel
> machines, I found recently they increased that to 16-20.
> The other thing you can try to st is the cache latencies, make sure that
> they are reasonable.
> For prefetcher, you can use IMPPrefetcher in addition to DCPT, it has a
> pretty aggressive stream prefetcher inside.
> Also, DRAM memory mapping is important, I do not remember what is the
> default for the the mem type you are using
>
> Majid
>
>
>
> On Sat, Apr 16, 2022 at 2:12 AM 王子聪  wrote:
>
>> Hi Majid,
>>
>> Thanks for your suggestion! I check the default number of MSHRs (in
>> configs/common/Caches.py), and found the default #MSHR of L1/L2 are 4 and
>> 20 respectively.
>>
>> According to the PACT’18 paper "Cimple: Instruction and Memory Level
>> Parallelism: A DSL for Uncovering ILP and MLP”,  it says that "Modern
>> processors typically have 6–10 L1 cache MSHRs”, and "Intel’s Haswell
>> microarchitecture uses 10 L1 MSHRs (Line Fill Buffers) for
>> handling outstanding L1 misses”. So I change to L1 #MSHRs to 16 and L2
>> #MSHRs to 32 (which I think it’s enough to handling outstanding misses),
>> and then change the L1/L2 prefetcher type to DCPT. Then I got the STREAM
>> output as shown in below:
>>
>> ./build/X86/gem5.opt configs/example/se.py --cpu-type=O3CPU --caches
>> --l1d_size=256kB --l1i_size=256kB
>> --param="system.cpu[0].dcache.mshrs=16;system.cpu[0].icache.mshrs=16;system.l2.mshrs=32"
>> --l2cache --l2_size=8MB --l1i-hwp-type=DCPTPrefetcher
>> --l1d-hwp-type=DCPTPrefetcher --l2-hwp-type=DCPTPrefetcher
>> --mem-type=DDR3_1600_8x8 -c ../stream/stream
>> -
>> FunctionBest Rate MB/s  Avg time Min time Max time
>> Copy:3479.8 0.004598 0.004598 0.004598
>> Scale:   3554.0 0.004502 0.004502 0.004502
>> Add: 4595.0 0.005223 0.005223 0.005223
>> Triad:   4705.9 0.005100 0.005100 0.005100
>> -
>>
>> The busutil of DRAM also improved:
>> -
>> system.mem_ctrls.dram.bytesRead  239947840  # Total bytes read
>> (Byte)
>> system.mem_ctrls.dram.bytesWritten   121160640  # Total bytes written
>> (Byte)
>> system.mem_ctrls.dram.avgRdBW  1611.266685  # Average DRAM read
>> bandwidth in MiBytes/s ((Byte/Second))
>> system.mem_ctrls.dram.avgWrBW   813.602251  # Average DRAM write
>> bandwidth in MiBytes/s ((Byte/Second))
>> system.mem_ctrls.dram.peakBW  12800.00  # Theoretical peak
>> bandwidth in MiByte/s ((Byte/Second))
>> system.mem_ctrls.dram.busUtil18.94  # Data bus
>> utilization in percentage (Ratio)
>> system.mem_ctrls.dram.busUtilRead12.59  # Data bus
>> utilization in percentage for reads (Ratio)
>> system.mem_ctrls.dram.busUtilWrite6.36  # Data bus
>> utilization in percentage for writes (Ratio)
>> system.mem_ctrls.dram.pageHitRate89.16  # Row buffer hit
>> rate, read and write combined (Ratio)
>> -
>>
>> It’s indeed improving the achieved bandwidth, but still a little far away
>> from the peak bandwidth of DDR3_1600 (12800 MiB/s). stats.txt is uploaded
>> for reference (
>> https://gist.github.com/wzc314/cf29275f853ee0b2fcd865f9b492c355)
>>
>> Any idea is appreciated!
>> Thank you in advance!
>>
>> Bests,
>> Zicong
>>
>>
>>
>> 2022年4月16日 00:08,Majid Jalili  写道:
>>
>> Hi,
>> Make sure your system has enough MSHRs, out of the box, L1, and L2 are
>> set to have a few MSHR entries.
>> Also, stride prefetcher is not the best, you may try something better:
>> DCPT gives me better numbers.
>>
>> On Fri, Apr 15, 2022 at 4:57 AM Zicong Wang via gem5-users <
>> gem5-users@gem5.org> wrote:
>> Hi Jason,
>>
>>   We are testing the memory bandwidth program STREAM ​(
>> https://www.cs.virginia.edu/stream/)​, 

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

2022-04-22 Thread Jason Lowe-Power via gem5-users
I just pushed a change that will make this error message better.

"fatal: Cannot instantiate an abstract SimObject (system.dev)" is what the
error now says :).

See https://gem5-review.googlesource.com/c/public/gem5/+/59049

Cheers,
Jason

On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Power 
wrote:

> Hello,
>
> I believe the problem is that gem5 tries to do too much automatically for
> you! gem5 automatically creates a lot of the constructor/destructor codes.
> Given all of this hidden/automatic code generation, it's difficult to know
> exactly what's going wrong (for both you and for us).
>
> That said, I think the problem is that `PioDevice` is an abstract
> SimObject, not a concrete SimObject. This may work if you instead use the
> `DmaDevice`.
>
> Cheers,
> Jason
>
> On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> By adding a PioDevice() to my version of two_level.py configuration
>> script, I get this error
>>
>>
>>
>> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>>
>> And checking io_device.cc the constructor looks empty
>>
>>
>>
>> Any help please? Thanks
>>
>>
>>
>> *Details:*
>>
>>
>>
>> Traceback (most recent call last):
>>   File "", line 1, in 
>>   File "build/X86/python/m5/main.py", line 455, in main
>> exec(filecode, scope)
>>
>>
>>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
>> 187, in 
>> m5.instantiate()
>>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>>
>>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
>> self.getCCParams()
>>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
>> cc_params = cc_params_struct()
>>
>> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>>
>>
>>
>>
>>
>> *Io_device.cc*
>>
>> include "dev/io_device.hh"
>>
>> #include "base/trace.hh"
>> #include "debug/AddrRanges.hh"
>> #include "sim/system.hh"
>>
>> namespace gem5
>> {
>>
>> PioDevice::PioDevice(const Params )
>> : ClockedObject(p), sys(p.system), pioPort(this)
>> {}
>>
>> PioDevice::~PioDevice()
>> {
>> }
>>
>>
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[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

2022-04-22 Thread Jason Lowe-Power via gem5-users
Hello,

I believe the problem is that gem5 tries to do too much automatically for
you! gem5 automatically creates a lot of the constructor/destructor codes.
Given all of this hidden/automatic code generation, it's difficult to know
exactly what's going wrong (for both you and for us).

That said, I think the problem is that `PioDevice` is an abstract
SimObject, not a concrete SimObject. This may work if you instead use the
`DmaDevice`.

Cheers,
Jason

On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
gem5-users@gem5.org> wrote:

> By adding a PioDevice() to my version of two_level.py configuration
> script, I get this error
>
>
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
> And checking io_device.cc the constructor looks empty
>
>
>
> Any help please? Thanks
>
>
>
> *Details:*
>
>
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
> exec(filecode, scope)
>
>
>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
> 187, in 
> m5.instantiate()
>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>
>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
> self.getCCParams()
>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
> cc_params = cc_params_struct()
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
>
>
>
>
> *Io_device.cc*
>
> include "dev/io_device.hh"
>
> #include "base/trace.hh"
> #include "debug/AddrRanges.hh"
> #include "sim/system.hh"
>
> namespace gem5
> {
>
> PioDevice::PioDevice(const Params )
> : ClockedObject(p), sys(p.system), pioPort(this)
> {}
>
> PioDevice::~PioDevice()
> {
> }
>
>
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[gem5-users] Re: Integrating MCPAT with gem5

2022-04-22 Thread Jason Lowe-Power via gem5-users
Hi Vipin,

McPAT is not the same kind of simulator as SST, DRAMSim, and SystemC, so it
cannot be integrated in the same way. It's not really a timing simulator at
all. You can use gem5's statistics output as the "activity rate" which is
one of the inputs to McPAT. However, the other inputs (e.g., the relative
energy cost of different activations) is not something that you can get
from gem5.

There have been a few scripts created to convert gem5 stats to McPAT files
in the past. However, I do not think that there are any that work with the
current version (21.2) of gem5. You may be able to find one and update it
for your needs.

Cheers,
Jason

On Thu, Apr 21, 2022 at 3:49 AM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> Simulators like SST, DRAMSim, SystemC can be integrated with gem5.
> Can we integrate the McPAT with gem5 ? Are there any pointers available
> for doing this?
>
> Thanks in advance.
>
> Regards,
> Vipin Patel
> Ph.D. CSE
> IIT Kanpur
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[gem5-users] Re: How to set the Cache replacement policy

2022-04-12 Thread Jason Lowe-Power via gem5-users
Hi Ankit,

I would suggest modifying your python runscript instead of using command
line parameters.
https://www.gem5.org/documentation/learning_gem5/introduction/ may help
explain how to set parameters on SimObjects.

Cheers,
Jason

On Wed, Apr 6, 2022 at 2:48 PM Ankit Berde  wrote:

> Hi Gem5 Team,
>
> Could you please guide us on how to set the replacement policy to a
> certain value. We are trying to simulate Cache Replacement policies, and
> whichever argument we provide as "--repl_policy==FIFORP()", it by default
> calls LRURP.
>
> Could you please help us on this
>
> Thanks,
> Ankit
>
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[gem5-users] Re: How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

2022-03-29 Thread Jason Lowe-Power via gem5-users
Hi Tom,

On Tue, Mar 29, 2022 at 9:39 AM tomjosekallooran--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi ,
> This may sound very generic, but i want to try some experiments with the
> out of order implementation. I came across few scenarios, which are listed
> below (any input would be helpful):
> 1. lets consider the following set of instructions (an example which was
> made up):
> Address instr  Operands
> 4357136cmp {"x1", "#16"}
> 4357140cmp {"x2", "#16"}
> 4357144bhi   {"4387895"}
>
> So if we have two execution units which can execute integer instructions,
> then both "cmp" instruction (4357136 and 4357140) could be issued to the
> execution unit. But an "cmp" instruction will update N,Z,C,V flags which
> inturn are used for evaluating conditional flags (eq_ne, hi_ls, cs_cc etc).
> So, can these two cmp be issued to execution units in the same cycle? If
> so, are the N,Z,C,V for each cmp only updated after inorder commit? How is
> it handled ? (do we use temp registers for holding each N,Z,C,V value?)
>

If I remember correctly, we rename all of the flag registers on each
instruction, and we increase the number of physical registers such that
this renaming is not a bottleneck. In a real processor, I don't think it
would work this way, but it should be OK performance-wise.


>
> 2. In speculative execution, how are stores implemented? do we place them
> into a store buffer and write it to memory once its commited?
>

I think that's correct, at least for x86. In Arm/RISC-V the stores could go
out of order to memory as well. You can check the code in the lsq_unit
files in src/cpu/o3 and poke around for "tso" to see exactly how it's
handled. Someone else may remember better than I do :).

Cheers,
Jason


>
> Any input would be appreciated.
> Regards,
> Tom
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[gem5-users] Re: Problem with SimObject

2022-03-28 Thread Jason Lowe-Power via gem5-users
Hi Artyom,

You're absolutely right that the tutorial needs to be updated! The
website is also open source and managed via a git repo:
https://gem5.googlesource.com/public/gem5-website/. Updating this would be
a good way to get started contributing to gem5 :).

By the way, for the namespace, you can also wrap the file in the following
so you don't have to explicitly use namespaces everywhere:

```
namespace gem5
{

}
```

Cheers,
Jason

On Sat, Mar 26, 2022 at 10:57 PM Artyom Liu via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> The problem is solved by literally adding a new parameter `sim_objects`.
>
>  > SimObject("HelloObject.py", sim_objects = ["HelloObject"])
>
> But I find yet another problem with the tutorial: the code that use
> classes from gem5 is missing namespace declaration. For example, the
> class `SimObject` is under namespace `gem5`, but the tutorial is using
> it directly. It makes the compiler unable to find the class.
>
> ```
> #ifndef __LEARNING_GEM5_HELLO_OBJECT_HH__
> #define __LEARNING_GEM5_HELLO_OBJECT_HH__
>
> #include "params/HelloObject.hh"
> #include "sim/sim_object.hh"
>
> class HelloObject : public SimObject
> {
>public:
>  HelloObject(const HelloObjectParams );
> };
>
> #endif // __LEARNING_GEM5_HELLO_OBJECT_HH__
> ```
>
> For the compiler to work, we should use `gem5::SimObject` instead. And
> `gem5::HelloObjectParams` for the same reason.
>
> None of the problems are mentioned in the tutorial. I wonder if it is
> necessary to *update* the tutorial?
>
> Artyom
> artyom...@hust.edu.cn
>
> On 3/27/22 10:05, Artyom Liu wrote:
> > Hi,
> >
> > I'm new to gem5 and just start learning by following the tutorial on
> > gem5.org. However, there's a problem when I try to create my custom
> > object[1].
> >
> > [1]: https://www.gem5.org/documentation/learning_gem5/part2/helloobject/
> >
> > I follow exactly the guide, but I fail to re-compile with scons. The
> > error message as below.
> >
> >  > Error: SimObject(HelloObject.py...) must list c++ sim_objects or
> > enums > (set either to [] if there are none).
> >
> > My gem5 version is Version 21.2.1.0, and I noticed that there's an *API
> > change* about SimObject declaration in Version 21.2.0.0, requiring that
> > sim_object parameter of SimObject declaration "should list all SimObject
> > classes which have a type attribute defined".
> >
> > It matches the error message. So I wonder how could I change my
> > SConscript to fit this change? My current SConscript is from the
> tutorial.
> >
> > ```
> > Import("*")
> >
> > SimObject("HelloObject.py")
> > Source("hello_object.py")
> > ```
> >
> > Artyom
> > artyom...@hust.edu.cn
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[gem5-users] Re: gem5 and non volatile memory

2022-03-25 Thread Jason Lowe-Power via gem5-users
Hello Taiyu,

I would suggest reaching out to the VANS authors. Since this project is not
part of the gem5 repository, we have little control over the integration.

Cheers,
Jason

On Thu, Mar 24, 2022 at 8:49 PM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:

> Could you give me some advise to integrate VANS with new version gem5?
> VANS is interrogated to commit id dde093b2 .
> However the newer version of gem5 breaks a lot of old Python interfaces,
> making it unable to run with VANS GEM5 wrapper, although compilation is
> fine.
> When I run VANS with new version gem5.
> The respond pkt can not sent via port.sendTimingResp.
>
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[gem5-users] Re: CXL protocol/model implementation

2022-03-25 Thread Jason Lowe-Power via gem5-users
Hi Zicong,

1. I personally don't believe that CXL in SE mode would be very
interesting. From  my point of view, CXL would be interesting only to
capture the OS and system-level effects. That said, you may be able to test
CXL.cache in SE mode.

2.
To implement the different protocols:
CXL.io: This would be extending the PCI devices in gem5/src/dev. This part
of the protocol will need to be implemented functionally to get the OS
drivers to work correctly.
CXL.mem: This should be quite straightforward to implement without any
changes to any coherence protocols. This part of CXL would just be setting
up the memory ranges correctly and hooking it into CXL.io. I would start
with this one.
CXL.cache: To model the coherence in CXL.cache, you will need to add and/or
modify a new Ruby coherence protocol. To get this to work, you'll first
have to have CXL.io and be able to figure out how to communicate the memory
ranges (like CXL.mem).

3.
CXLDevice would most likely inherit from PciDevice. The other devices would
be whatever you want them to be (e.g., a GPU which speaks CXL.cache or a
memory device that speaks CXL.mem). Then these devices would "register"
with the CXLDevice and through the configuration file you will hook up the
other devices in the protocol.

The most complex part of all of this will be the configuration. I would
suggest trying to make the configuration as modular as possible. The
examples in the standard library should help.

I've given this some thought, but I haven't started implementing anything.
I'm sure that the process I outlined above will change as you start diving
into things.

Cheers,
Jason

On Fri, Mar 25, 2022 at 1:35 AM Zicong Wang via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
>  We are planning to implement and test CXL protocol/model with gem5, and
> I've seen your reply about CXL implementation (
> https://www.mail-archive.com/gem5-users@gem5.org/msg18881.html). Before
> diving into the code, I have some questions about implementation. Could you
> please provide some tips? Thanks!​
>
>  1. Could it be implemented in SE mode? It seems to be complicated with
> the OS layer and driver layer in FS mode, and we want to firstly implement
> an initial model (e.g., a type 1 (cxl.io + cxl.cache) or type 3 (cxl.io +
> cxl.mem) device) as simple as possible.
>
>  2. Could the cxl.cache/mem sub-protocol ​be implemented in SLICC? How to
> treat and implement the cxl.io sub-protocol (which is PCIe-like)?
>
>  3. What kind of SimObject should be implemented roughly (CXLDevice,
> CXLController, etc.)?​ Should the CXLDevice be inherited from PciDevice
> class?
>
>  Thank you very much!
>
>
> Best Regards,
>
> Zicong Wang
>
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[gem5-users] Re: Issue with strange virtual address access

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hi Tom,

I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags
which may help figure it out. It's possible that's the address of a
dynamically-loaded library as well.

Also, this trace looks like it came from Arm instead of x86. I don't
have as much experience looking at Arm addresses and guessing the meaning
:).

Cheers,
Jason

On Tue, Mar 22, 2022 at 8:32 AM tomjosekallooran--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
> I have one doubt.
> The following is some selected parts of Exec trace:
> If we look at lines:
> line 4:   ldr   x1, [sp]: MemRead :
> D=0x0001
> A=0x7efe70
> line 74  :   ldr   x1, [x0]: MemRead :
> D=0x0010
> A=0x7efe90
> line 88  :   ldr   x3, [x8, #3840]: MemRead :  D=0x0001
> A=0x498f00
> line 92  :   ldr   x7, [x10, #3896]  : MemRead :  D=0x0001
> A=0x499f38
> line 152:   ldr   x28, [x0, #8]: MemRead :  D=0x004471e3
> A=0x7efe98
>
> Prior to these lines, there was no MemWrite to the corresponding address.
> Is this also related to Stack addresses?Could you please provide an insight
> on how these addresses are loaded with these data?
>
> Any information on the same would hugely help.
>
> Regards,
> Tom
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[gem5-users] Re: Building Old gem5 error

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hello Abdelrahman,

Unfortunately, it's incredibly difficult to keep the development
environment for older versions of gem5 working. You may be able to find an
old dockerfile in those gem5 repositories that could help to recreate the
build environment. (I'm not sure if we were using docker at the time or
not.)

Another thing you can try is specifying a python version when running
scons. You can use
```
python2 `which scons` build/X86_MESI_Two_Level/gem5.opt
```
That should force scons to use python2. However, you might find that the
scons version that you installed only works with python3. Again, it's
really hard to get these older gem5's to build on modern systems.

If those two ideas don't work, a final suggestion would be to create a
docker container (or install) Ubuntu 16.04 and try with that. 16.04
should have everything python2 by default.

Good luck!

Cheers,
Jason

On Tue, Mar 22, 2022 at 3:19 AM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to build older version(s) of gem5 (specifically, the ones used
> for InvisiSpec and STT). I understand that this version of gem5 requires
> python2, thus, I build a virtual environment based on python2 and
> re-installed scons. However, when I run this command:
> scons build/X86_MESI_Two_Level/gem5.opt -j16
>
> I got the following error:
>
> AttributeError: 'NoneType' object has no attribute 'group':
>   File "stt/SConstruct", line 435:
> *if not as_version or compareVersions(as_version, "2.23") < 0:*
>   File "stt/src/python/m5/util/__init__.py", line 133:
> v1 = make_version_list(v1)
>   File "stt/src/python/m5/util/__init__.py", line 127:
> return map(lambda x: int(re.match('\d+', x).group()), v.split('.'))
>   File "stt/src/python/m5/util/__init__.py", line 127:
> return map(lambda x: int(re.match('\d+', x).group()), v.split('.'))
>
> Same with InvisiSpec.
>
> Before line 435@stt/SConstruct, which is underlined above, line 433 has
> the following:
> as_version = as_version_raw[-1].split('-')[0] if as_version_raw else None
>
> When I printed as_version, its value was:
> same
>
> How can I solve this problem? Or, what further information do you need me
> to share?
>
> Thank you!
>
> --
>
> *Best,Abdelrahman Hussein*
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[gem5-users] Re: Issue with strange virtual address access

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hi Liyan,

This looks like a stack address to me, so it won't appear in the objdump.

Since you're using SE mode, gem5 is controlling the physical address
mappings (not the OS). You can use the "Vma" debug flag to see all of the
virtual memory areas that gem5 creates/assigns. the "SyscallVerbose" flag
could also be useful.

Cheers,
Jason

On Mon, Mar 21, 2022 at 12:46 AM liyan.chen--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I used the following command to view the virtual address translation
> process.
>
>   build/X86/gem5.opt --debug-flags=Exec,TLB
> --debug-file=/home/liyan/Desktop/gem5/m5out/debug.txt configs/example/se.py
> --cpu-type=TimingSimpleCPU --caches --l2cache --mem-type=DRAMsim3
> --num-cpus=1 -c "tests/test-progs/hello/bin/x86/linux/hello"
>
> However, I found some strange virtual address such as 0x7fffee20
>
>   56500: system.cpu.dtb: Translating vaddr 0x7fffee20.
>   56500: system.cpu.dtb: In protected mode.
>   56500: system.cpu.dtb: Paging enabled.
>   56500: system.cpu.dtb: Handling a TLB miss for address 0x7fffee20 at
> pc 0x400a55.
>   56500: system.cpu.dtb: Mapping 0x7fffe000 to 0xbd000
>   56500: system.cpu.dtb: Miss was serviced.
>   56500: system.cpu.dtb: Entry found with paddr 0xbd000, doing protection
> checks.
>   56500: system.cpu.dtb: Translated 0x7fffee20 -> 0xbde20.
>
> And it(0x7fffee20) also appears here(I don't know whether there is any
> relationship)
>
>   56500: system.cpu T0 : @_start+5: pop rsi
>   56500: system.cpu T0 : @_start+5.0  :   POP_R : ldis   t1, SS:[rsp] :
> MemRead :  D=0x0001 A=0x7fffee20
>  110500: system.cpu T0 : @_start+5.1  :   POP_R : addi   rsp, rsp, 0x8 :
> IntAlu :  D=0x7fffee28
>  110500: system.cpu T0 : @_start+5.2  :   POP_R : mov   rsi, rsi, t1 :
> IntAlu :  D=0x0001
>
> Then I used following command to check the address in hello.dump file but
> didn't find such address.
>
>   objdump -D hello > hello.dump
>
> I'm not familiar with the compilation process and work flow of the core.
> Does anyone know why these address exist?
>
> Any ideas are appreciated! Please reply if you have some advice. Thanks in
> advance!
>
> Liyan Chen
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[gem5-users] Re: How do I disable most statistics in the stats.txt under Atomic CPU

2022-03-17 Thread Jason Lowe-Power via gem5-users
Hello,

I don't believe there's a way to do that right now. However, in atomic
mode, many stats *are* skipped as they are only accessed in the "timing"
functions. I doubt it would make much performance difference. However,
that's just a guess, and I could be wrong.

Cheers,
Jason

On Wed, Mar 16, 2022 at 6:25 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  In the Atomic CPU, only a function simulation is performed for
> enabling or debugging applications. The performance statistics of the
> architecture are not concerned. Therefore, only a small items are required,
> e.g. number of instructions or cycles.
>
>
>
> According to my understanding, each performance measurement item in the
> code may affect the simulation speed. If we can disable statistics items
> that are not concerned in most functional models, the simulation speed may
> be greatly improved. I do not know whether my understanding is correct. If
> so, does GEM5 consider the performance statistics switch?
>
>
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[gem5-users] Re: Is thread lock not working under both SE and FS mode?

2022-03-14 Thread Jason Lowe-Power via gem5-users
Hi Meng,

It depends on the ISA you're using and the configuration of the system. For
instance, x86+classic caches is known to have some synchronization issues.
The transactional memory support only works with Arm, and I'm not sure
which memory system it requires.

What system are you trying to simulate?

Cheers,
Jason

On Sat, Mar 12, 2022 at 11:45 PM Chen Meng via gem5-users <
gem5-users@gem5.org> wrote:

> Hi!
>
> I was trying to run a multi-threaded program with thread locks, I tried
> many methods but only to result in failure. I borrowed the program code
> with thread lock from the following page:
> https://www.gem5.org/project/2020/10/27/tme.html , and it turns out to be
> unstable when I run it with FS mode.
>
> My gem5 version is v21.1.0.2, and my script is borrowed from
> gem5_resources also at v21.1.0.2 (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2),
> everything is stick to the SPEC-2017 tutorial (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2/src/spec-2017/README.md),
> except that I substitute the SPEC benchmarks with my own program.
>
> Any ideas are appreciated! Please reply if you have some advice or
> face/have faced the same problem. Thanks!
>
> Best Regards,
> Meng
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[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

2022-03-10 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman,


> Is there a better way you can suggest using SPEC2017 in FS mode to
> evaluate my system on gem5?
>

No, there's not a better way, as far as I know :).


> My understanding is that the FS simulation is significantly slow. Any
> guidelines on how to make it as fast as possible?


You can use sampling methodologies, but there are tradeoffs there. You can
run different simulation configurations in parallel as well. Generally,
there's nothing easy to do to improve simulation speed.

Jason

On Thu, Mar 10, 2022 at 7:17 AM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Thank you so much.
>
> There were some questions that you missed at the end of the email. I list
> them below again for convenience:
>
>
>- Is there a better way you can suggest using SPEC2017 in FS mode to
>evaluate my system on gem5?
>- My understanding is that the FS simulation is significantly slow.
>Any guidelines on how to make it as fast as possible?
>
> Above all, thanks a lot for taking time helping us. Much appreciated!
>
>
>
>
> On Thu, Mar 10, 2022 at 7:01 AM Jason Lowe-Power 
> wrote:
>
>> Hi Abdelrahman,
>>
>> From the get error message, it says:
>> "This error may be caused by a too restrictive setting
>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>   The default value was changed to 2 in kernel 4.6
>>   A value greater than 1 prevents gem5 from making
>>   the syscall to perf_event_open"
>>
>> If you put `1` or `0` in /proc/sys/kernel/perf_event_paranoid it should
>> work.
>>
>> Cheers,
>> Jason
>>
>> On Wed, Mar 9, 2022 at 9:27 PM Abdelrahman S. Hussein <
>> abdelrahman.sob...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am trying to run gem5 in FS mode using the following command (I am
>>> using gem5 v21.2):
>>>
>>> gem5/build/X86/gem5.opt
>>> gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
>>> spec-2017/disk-image/spec-2017/spec-2017-image/spec-2017 --benchmark
>>> 503.bwaves_r --size test
>>>
>>> However, I got the following error (There are details after the error,
>>> please continue reading after you check the error):
>>>
>>> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
>>> simulation...
>>> build/X86/cpu/kvm/perfevent.cc:176: panic: PerfKvmCounter::attach
>>> recieved error EACCESS
>>>   This error may be caused by a too restrictive setting
>>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>>   The default value was changed to 2 in kernel 4.6
>>>   A value greater than 1 prevents gem5 from making
>>>   the syscall to perf_event_open
>>> Memory Usage: 3817816 KBytes
>>> build/X86/cpu/kvm/perfevent.ccProgram aborted at tick 0
>>> :176: panic: PerfKvmCounter::attach recieved error EACCESS
>>>   This error may be caused by a too restrictive setting
>>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>>   The default value was changed to 2 in kernel 4.6
>>>   A value greater than 1 prevents gem5 from making
>>>   the syscall to perf_event_open
>>> Memory Usage: 3817816 KBytes
>>> ./spec_fs_run.sh: line 16: 1648681 Aborted
>>>
>>> I have done some checking:
>>>
>>>- Ran kvm-ok to make sure that KVM is working:
>>>$kvm-ok
>>>INFO: /dev/kvm exists
>>>KVM acceleration can be used
>>>
>>>- Also, I checked the value
>>>inside /proc/sys/kernel/perf_event_paranoid
>>>$cat /proc/sys/kernel/perf_event_paranoid
>>>3
>>>
>>>- The SPEC17 is created by following the instructions in:
>>>https://gem5art.readthedocs.io/en/v1.0.0/tutorials/spec2017-tutorial.html
>>>
>>>
>>> Questions:
>>>
>>>- How to solve this error?
>>>
>>>- Is it safe to modify the /proc/sys/kernel/perf_event_paranoid of
>>>the linux running on my host machine to 1, in case this solves the 
>>> problem?
>>>
>>>- Is there a better way you can suggest using SPEC2017 in FS mode to
>>>evaluate my system on gem5?
>>>
>>>
>>>
>>> Thanks.
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>>
>> --
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

2022-03-10 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman,

>From the get error message, it says:
"This error may be caused by a too restrictive setting
  in the file '/proc/sys/kernel/perf_event_paranoid'
  The default value was changed to 2 in kernel 4.6
  A value greater than 1 prevents gem5 from making
  the syscall to perf_event_open"

If you put `1` or `0` in /proc/sys/kernel/perf_event_paranoid it should
work.

Cheers,
Jason

On Wed, Mar 9, 2022 at 9:27 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hello,
>
> I am trying to run gem5 in FS mode using the following command (I am using
> gem5 v21.2):
>
> gem5/build/X86/gem5.opt
> gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> spec-2017/disk-image/spec-2017/spec-2017-image/spec-2017 --benchmark
> 503.bwaves_r --size test
>
> However, I got the following error (There are details after the error,
> please continue reading after you check the error):
>
> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
> build/X86/cpu/kvm/perfevent.cc:176: panic: PerfKvmCounter::attach recieved
> error EACCESS
>   This error may be caused by a too restrictive setting
>   in the file '/proc/sys/kernel/perf_event_paranoid'
>   The default value was changed to 2 in kernel 4.6
>   A value greater than 1 prevents gem5 from making
>   the syscall to perf_event_open
> Memory Usage: 3817816 KBytes
> build/X86/cpu/kvm/perfevent.ccProgram aborted at tick 0
> :176: panic: PerfKvmCounter::attach recieved error EACCESS
>   This error may be caused by a too restrictive setting
>   in the file '/proc/sys/kernel/perf_event_paranoid'
>   The default value was changed to 2 in kernel 4.6
>   A value greater than 1 prevents gem5 from making
>   the syscall to perf_event_open
> Memory Usage: 3817816 KBytes
> ./spec_fs_run.sh: line 16: 1648681 Aborted
>
> I have done some checking:
>
>- Ran kvm-ok to make sure that KVM is working:
>$kvm-ok
>INFO: /dev/kvm exists
>KVM acceleration can be used
>
>- Also, I checked the value inside /proc/sys/kernel/perf_event_paranoid
>$cat /proc/sys/kernel/perf_event_paranoid
>3
>
>- The SPEC17 is created by following the instructions in:
>https://gem5art.readthedocs.io/en/v1.0.0/tutorials/spec2017-tutorial.html
>
>
> Questions:
>
>- How to solve this error?
>
>- Is it safe to modify the /proc/sys/kernel/perf_event_paranoid of the
>linux running on my host machine to 1, in case this solves the problem?
>
>- Is there a better way you can suggest using SPEC2017 in FS mode to
>evaluate my system on gem5?
>
>
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: M5 Fs utility workbegin

2022-03-09 Thread Jason Lowe-Power via gem5-users
Great question!

Since KVM is executing using the host's hardware, you can't use the magic
instructions! However, we have another interface (called `m5_addr` or
`m5-addr` in the code, IIRC) that will work with KVM. If you compile using
-DM5_ADDR=, it should work in KVM. For x86, we usually
use 0x. Then, I believe you need to call a function to map
the memory (not sure what it's called, it's not in the documentation)
before calling any m5 functions.

See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
for an example.
Also see
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/Makefile.shared#9
for how we compile the parsec hooks with m5 addr.

Note: it looks like either parsec is a bit out of date with current gem5
develop or the README.md in util/m5 is out of date. I'm not sure which.

Cheers,
Jason

On Wed, Mar 9, 2022 at 4:47 PM George Michelogiannakis <
mixelog...@yahoo.co.uk> wrote:

> Hello Jason and everyone,
>
> I'll add the fix to my todo list :)
>
> But before then, I'm confused by something. Thanks for the link to hooks
> and indeed I "m5_work_begin(0,0);. I recompiled the benchmarks I had with
> work begin and end. It's just adding "m5_work_begin(0,0)" and 
> "m5_work_end(0,0)"
> at the right spots, without anything else fancy. It compiles and links
> fine. When I try to run natively as expected they terminate due to an
> illegal instruction ("./run: line 1:  1161 Illegal instruction").
> However, the exact same error happens if I run the same binary in FS mode.
> Note that I'm running first in KVM mode on a x86 host hoping to switch CPUs
> once the work start event happens. Are magic ops unsupported in KVM mode?
>
> Thanks!
>
>
> On Wednesday, March 9, 2022, 09:14:24 AM PST, Jason Lowe-Power via
> gem5-users  wrote:
>
>
> Hi George,
>
> For workbegin/workend, they can be called from within applications if you
> link to the libm5 library. For instance, in the parsec resource here:
> https://resources.gem5.org/resources/parsec we use the m5_workbegin()
> function in the ROI hooks. See
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
> for the code.
>
> This works in both SE mode and FS mode. I have no idea why those functions
> are not available in the m5 binary. This seems like an oversight, and it
> should be a simple fix. If you want to make the fix, we'd appreciate it,
> otherwise, we'll put it on the to do list :).
>
> If you require using the m5 binary without any changes, then you can use
> `m5 exit` and modify your run script to "understand" that the first exit is
> to reset the stats, the second exit means to dump the stats, etc.
>
> Cheers,
> Jason
>
> On Wed, Mar 9, 2022 at 4:08 AM Gabe Black via gem5-users <
> gem5-users@gem5.org> wrote:
>
> I don't think we ever transitioned from an assembly based mechanism to a C
> based one, since we have always (as far as I know) used both, assembly to
> actually invoke the call into gem5, and C to provide a friendly
> interface/wrapper around the assembly. That said, yes, it looks like work
> begin and work end are just not in the utility, but they are in the header
> files and are implemented in gem5 itself.
>
> Looking at this again triggered a vague memory where I think these didn't
> make sense being called from the utility for some reason? Maybe they only
> make sense in SE mode, or they should be called from code directly instead
> of from a shell or script? I'm not very familiar with them so I can't say
> for sure, but I vaguely remember there was something like that.
>
> Gabe
>
> On Wed, Mar 9, 2022 at 2:45 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi George,
>
>
>
> Thanks for reporting this, I noticed the same issue. When we transitioned
> from the old m5 subsystem (assembly based) to the new C based one we forgot
> to provide an implementation for workbegin and workend I suppose. Putting
> Gabe on CC
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> *From: *George Michelogiannakis via gem5-users 
> *Date: *Wednesday, 9 March 2022 at 06:54
> *To: *gem5-users@gem5.org 
> *Cc: *George Michelogiannakis 
> *Subject: *[gem5-users] M5 Fs utility workbegin
>
> Hello Gem5 community,
>
>
>
> I'm trying to use the M5 utility meant for full system mode to signal work
> begin and end. I see in the documentation that the utility supports these
> parameters:
>
>
>
>-

[gem5-users] Re: M5 Fs utility workbegin

2022-03-09 Thread Jason Lowe-Power via gem5-users
Hi George,

For workbegin/workend, they can be called from within applications if you
link to the libm5 library. For instance, in the parsec resource here:
https://resources.gem5.org/resources/parsec we use the m5_workbegin()
function in the ROI hooks. See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
for the code.

This works in both SE mode and FS mode. I have no idea why those functions
are not available in the m5 binary. This seems like an oversight, and it
should be a simple fix. If you want to make the fix, we'd appreciate it,
otherwise, we'll put it on the to do list :).

If you require using the m5 binary without any changes, then you can use
`m5 exit` and modify your run script to "understand" that the first exit is
to reset the stats, the second exit means to dump the stats, etc.

Cheers,
Jason

On Wed, Mar 9, 2022 at 4:08 AM Gabe Black via gem5-users <
gem5-users@gem5.org> wrote:

> I don't think we ever transitioned from an assembly based mechanism to a C
> based one, since we have always (as far as I know) used both, assembly to
> actually invoke the call into gem5, and C to provide a friendly
> interface/wrapper around the assembly. That said, yes, it looks like work
> begin and work end are just not in the utility, but they are in the header
> files and are implemented in gem5 itself.
>
> Looking at this again triggered a vague memory where I think these didn't
> make sense being called from the utility for some reason? Maybe they only
> make sense in SE mode, or they should be called from code directly instead
> of from a shell or script? I'm not very familiar with them so I can't say
> for sure, but I vaguely remember there was something like that.
>
> Gabe
>
> On Wed, Mar 9, 2022 at 2:45 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
>> Hi George,
>>
>>
>>
>> Thanks for reporting this, I noticed the same issue. When we transitioned
>> from the old m5 subsystem (assembly based) to the new C based one we forgot
>> to provide an implementation for workbegin and workend I suppose. Putting
>> Gabe on CC
>>
>>
>>
>> Kind Regards
>>
>>
>>
>> Giacomo
>>
>>
>>
>> *From: *George Michelogiannakis via gem5-users 
>> *Date: *Wednesday, 9 March 2022 at 06:54
>> *To: *gem5-users@gem5.org 
>> *Cc: *George Michelogiannakis 
>> *Subject: *[gem5-users] M5 Fs utility workbegin
>>
>> Hello Gem5 community,
>>
>>
>>
>> I'm trying to use the M5 utility meant for full system mode to signal
>> work begin and end. I see in the documentation that the utility supports
>> these parameters:
>>
>>
>>
>>- workbegin: Cause an exit evet of type, “workbegin”, that could be
>>used to mark the begining of an ROI.
>>- workend: Cause an exit event of type, “workend”, that could be used
>>to mark the termination of an ROI.
>>
>> But when I run the utility in X86 after compiling it for X86 those two
>> options aren't available as commands. There is a "fail" option with a
>> parameter that isn't mentioned in the documentation. Is that the way to
>> simulate workbegin and workend?
>>
>>
>>
>> Thanks in advance,
>>
>>   George M
>>
>>
>>
>>
>> IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
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>>
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[gem5-users] Re: Inquiry on the gem5 communities and forums

2022-02-18 Thread Jason Lowe-Power via gem5-users
Hi Jianda,

There will also be a tutorial and workshop at ISCA in New York this year
(June 11). More info coming soon!

Cheers,
Jason

On Fri, Feb 18, 2022 at 8:21 AM Gabriel Busnot via gem5-users <
gem5-users@gem5.org> wrote:

> Hi and welcome Jianda,
>
> You are in the right place! Feel free to subscribe to this mailing list to
> get notified upon new post. You can also post any question related to gem5.
> You will usually get an answer within a working day or two. You can also
> monitor the Jira to learn about what is going on in the background (
> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues).
>
> Best,
> Gabriel
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[gem5-users] Re: Not able to access webpage to run_npb.py

2022-02-17 Thread Jason Lowe-Power via gem5-users
Hi David,

Sorry for the confusion. We need to update that documentation! You can now
find the script here:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/example/gem5_library/x86-npb-benchmarks.py
(or in configs/example/gem5_library in the gem5 repo).

Cheers,
Jason

On Thu, Feb 17, 2022 at 10:42 AM David Fong via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
>
>
> I’m going through the steps to create the npb environment.
>
>
>
> https://www.gem5.org/documentation/gem5art/tutorials/npb-tutorial
>
>
> gem5 run scripts
>
> Next, we need to add gem5 run scripts. We will do that in a folder named
> configs-npb-tests. Get the run script named run_npb.py from here
> ,
> and other system configuration files from [here]((
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/npb/configs/system/
> ).
>
>
>
>
>
> I’m not able to access the link to “run_npb.py”.
>
>
>
>
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/npb/configs/run_npb.py
>
>
>
> I get this error
>
>
>
>
>
> Does anyone else have this problem and how to workaround ?
>
> Is there another location to download the “run_npb.py” ?
>
>
>
> Thanks,
>
>
>
> David
>
>
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[gem5-users] Re: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

2022-02-16 Thread Jason Lowe-Power via gem5-users
Hello,

This specific setup has not been tested, as far as I know. I would also
suggest using v21.2.1 as there have been lots of bugfixes to CHI in the
past year.

Cheers,
Jason

On Tue, Feb 15, 2022 at 6:23 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in
> Ruby-CHI and O3?
>
> Or if anyone has ever bootup with it?
>
>
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[gem5-users] Re: Run srsRAN code with gem5

2022-02-11 Thread Jason Lowe-Power via gem5-users
Hi Uma,

Not all X86 vector instructions are implemented. What you're seeing is
that pmovzxbw isn't
implemented. Specifically, there's at least one version (as shown here
https://www.felixcloutier.com/x86/pmovzx) which hasn't been implemented
yet. I'm not sure which one. The `Vdq_Udq_or_Mq` somehow specifies the
sizes of the registers, but it's not documented and you'll have to dig into
the code to figure out how it works.

You can either compile your code with SSE4/AVX or you can implement the
instruction. If you do the latter, we would appreciate the contribution!

Cheers,
Jason

On Fri, Feb 11, 2022 at 5:13 AM VEDIKA JITENDRA KULKARNI via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
>
> *We are trying to run srsRAN functionalities individually as srsepc,srsenb
> and srsUE. Also I need suggestions on how to run end-end srsRAN code into
> gem5 to analyse the ARM vs X86 performance. *
>
>
> *Please find the below error for srsENB while simulating in gem5.*
>
>
>
> command line: ./build/X86/gem5.opt configs/example/se.py
> --cmd=tests/test-progs/hello/bin/x86/linux/srsenb
>
>
>
> Global frequency set at 1 ticks per second
>
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
>
> build/X86/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
>  REAL SIMULATION 
>
> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
>
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall
> set_robust_list(...)
>
> build/X86/sim/syscall_emul.cc:85: warn: ignoring syscall rt_sigaction(...)
>
>   (further warnings will be suppressed)
>
> build/X86/sim/syscall_emul.cc:85: warn: ignoring syscall
> rt_sigprocmask(...)
>
>   (further warnings will be suppressed)
>
> build/X86/sim/syscall_emul.hh:509: warn: futex: op 7 not implemented;
> ignoring.
>
>
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/arch/x86/generated/exec-ns.cc.inc:27: warn: instruction
> 'pmovzxbw_Vdq_Udq_or_Mq' unimplemented
>
> *build/X86/arch/x86/faults.cc:129: panic: Unrecognized/invalid instruction
> executed:*
>
>
>
> {
>
> leg = 0x10,
>
> rex = 0,
>
> vex/xop = 0x5,
>
> op = {
>
> type = three byte 0f38,
>
> op = 0x59,
>
> },
>
> modRM = 0,
>
> sib = 0,
>
> immediate = 0,
>
> displacement = 0
>
> dispSize = 0}
>
> Memory Usage: 842444 KBytes
>
> Program aborted at tick 7880406000
>
> --- BEGIN LIBC BACKTRACE ---
>
> ./build/X86/gem5.opt(+0x67429c)[0x5620be8bc29c]
>
> ./build/X86/gem5.opt(+0x6a0eaa)[0x5620be8e8eaa]
>
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1b35eeb980]
>
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1b34d3efb7]
>
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1b34d40921]
>
> ./build/X86/gem5.opt(+0x342b6f)[0x5620be58ab6f]
>
> ./build/X86/gem5.opt(+0x74f8b7)[0x5620be9978b7]
>
> ./build/X86/gem5.opt(+0xe9218a)[0x5620bf0da18a]
>
> ./build/X86/gem5.opt(+0xe7f779)[0x5620bf0c7779]
>
> ./build/X86/gem5.opt(+0x680fee)[0x5620be8c8fee]
>
> ./build/X86/gem5.opt(+0x6c5fd4)[0x5620be90dfd4]
>
> ./build/X86/gem5.opt(+0x6c6d1e)[0x5620be90ed1e]
>
> ./build/X86/gem5.opt(+0xc2b44a)[0x5620bee7344a]
>
> ./build/X86/gem5.opt(+0x69ced9)[0x5620be8e4ed9]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyCFunction_Call+0x96)[0x7f1b3630b736]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x76e0)[0x7f1b3627cb20]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f1b36273a0f]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f1b362740fc]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f1b3627a303]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17a803)[0x7f1b36272803]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c2be)[0x7f1b362742be]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f1b3627a303]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f1b36273a0f]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f1b362740fc]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f1b3627a303]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f1b36273a0f]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f1b362744ce]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCode+0x1b)[0x7f1b3627524b]
>
> 

[gem5-users] Re: findOrCreate function

2022-02-09 Thread Jason Lowe-Power via gem5-users
Hi Scott,

I think the answer is the same as the prior email. You need to register an
exit callback to close the file stream :). See, for instance, the elastic
trace code:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/cpu/o3/probe/elastic_trace.cc#103

Cheers,
Jason

On Wed, Feb 9, 2022 at 5:19 PM Scott Blankenberg via gem5-users <
gem5-users@gem5.org> wrote:

> Hello all,
>
> Has anyone used the findOrCreate Gem5 function for opening custom file
> streams?
>
> For example in src/cpu/base.cc we see that this function is used in the
> constructor for BaseCPU
>
>   const std::string fname = csprintf("ftrace.%s", name());
>   functionTraceStream = simout.findOrCreate(fname)->stream();
>
>
> Has anyone who has used this function called it to create .gz files?
>
> I am having an issue right now where for some benchmarks I run that the
> final gz file I get out is not compressed correctly. When I attempt to
> decompress the .gz files, I will get errors such as "unexpected end of
> file".
>
> One possibility I can think of is that the file does not close properly.
> However, I am struggling to find out where I should close the file since I
> need to do it at the end of the simulation and there is no clear place in
> BaseCPU code to place code you want to execute at the end of simulation. I
> have tried using the BaseCPU destructor to close my stream files, but the
> code I put into this destructor does not seemed to be invoked.
>
> Anyways, has anyone ran into similar issues?
>
> Thanks,
>
> Scott Blankenberg
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[gem5-users] Re: Destructor for BaseCPU

2022-02-09 Thread Jason Lowe-Power via gem5-users
Hi Scott,

If you want something to execute before gem5 is completed, you can call
`registerExitCallback`. See
http://doxygen.gem5.org/release/current/namespacegem5.html#abcf3056836ee522620e5b14d9392ea87

I *think* that will solve your problem, but let me know if not. I don't
think there's a clean way to have a SimObject's destructor guaranteed to be
called.

Cheers,
Jason

On Wed, Feb 9, 2022 at 4:47 PM Scott Blankenberg via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> In src/cpu/base.cc we have the following destructor:
>
> BaseCPU::~BaseCPU()
> {
> }
>
> By default nothing is inside of it. However, when I put code inside, it
> does not seem to be executed at any point. Based on some previous threads I
> have seen on the forums, it seems that the destructor for BaseCPU is not
> being called at the end of the simulation.
>
> Has anyone found a way to make sure this destructor is called when the
> simulation ends?
>
> Similarly, has anyone written a tracer which is a subclass of InstTracer
> that has a destructor which is successfully called at the end of
> simulation?
>
> Basically my objective is to make sure the destructor to my customTracer
> is called at the end of the simulation.
>
> Thanks,
>
> Scott Blankenberg
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[gem5-users] Re: Problems on creating HelloObject & re-compiling following tutorial

2022-02-02 Thread Jason Lowe-Power via gem5-users
Namespaces were recently added to gem5 and the documentation hasn't been
updated, yet. We'll put that on the to do list.

Cheers,
Jason

On Wed, Feb 2, 2022 at 6:11 AM Zhang Zhiyuan via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 faculties:
>
> Hi! I’ve been trying to follow the getting started guide on the gem5
> website, and encountered this question in “Creating a very simple
> SimObject” part of the tutorial. I removed the files under
> src/learning_gem5/part2, and substituted them with the following files,
> content of which are precisely copied down from the tutorial:
>
> However, when I tried to recompile the gem5.opt, the following error was
> shown:
>
>
>
> In file included from build/X86/learning_gem5/part_new/hello_object.cc:2:
>
> build/X86/learning_gem5/part_new/hello_object.hh:8:1: error: expected
> class-name before '{' token
>
> 8 | {
>
>   | ^
>
> build/X86/learning_gem5/part_new/hello_object.hh:10:27: error:
> 'HelloObjectParams' does not name a type; did you mean 'HelloObject'?
>
>10 | HelloObject(const HelloObjectParams );
>
>   |   ^
>
>   |   HelloObject
>
> build/X86/learning_gem5/part_new/hello_object.cc:6:32: error:
> 'HelloObjectParams' does not name a type; did you mean 'HelloObject'?
>
> 6 | HelloObject::HelloObject(const HelloObjectParams ) : SimObject(p)
>
>   |^
>
>   |HelloObject
>
> build/X86/learning_gem5/part_new/hello_object.cc: In constructor
> 'HelloObject::HelloObject(const int&)':
>
> build/X86/learning_gem5/part_new/hello_object.cc:6:56: error: class
> 'HelloObject' does not have any field named 'SimObject'
>
> 6 | HelloObject::HelloObject(const HelloObjectParams ) : SimObject(p)
>
>   |^
>
> [SO Param] m5.objects.Ethernet, EtherLink -> X86/params/EtherLink.hh
>
> [SO Param] m5.objects.Ethernet, DistEtherLink ->
> X86/params/DistEtherLink.hh
>
> [SO Param] m5.objects.Ethernet, Sinic -> X86/params/Sinic.hh
>
> [SO Param] m5.objects.FuncUnit, FUDesc -> X86/params/FUDesc.hh
>
> [SO Param] m5.objects.InstPBTrace, InstPBTrace -> X86/params/InstPBTrace.hh
>
> scons: *** [build/X86/learning_gem5/part_new/hello_object.o] Error 1
>
> scons: building terminated because of errors.
>
>
>
> It seems that the HelloObject sources cant find HelloObjectParams and
> SimObject definitions. However, after throwing everything in the header and
> the source file under namespace gem5, and adding cxx_class member in the
> python class definition, everything seems to work out fine. So is it an
> issue that needs to be fixed in the tutorial, or is the namespace inclusion
> unnecessary here? Thanks!
>
>
>
>  Zhiyuan Zhang
>
>
>
>  2022.2.2
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[gem5-users] Re: Clarification minor CPU “in-order”

2022-01-29 Thread Jason Lowe-Power via gem5-users
Good question, Felix!

The short answer is that since there are instructions that take multiple
cycles to execute you need something like a scoreboard to track the
dependencies.

In the H book, you can see some details of this in Appendix C.5 (6th
edition). If you happen to have the Patterson and Hennessy Computer
Organization and Design book, Section 4.11 (2nd ed. of RISC-V version,
titled "Real Stuff: The ARM Cortex-A53...") shows a pipeline very similar
to the minor CPU.

Cheers,
Jason

On Sat, Jan 29, 2022 at 4:06 PM Felix Böseler via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everybody,
>
> According to [1] the gem5 minor CPU is an in-order processor model and
> features a scoreboarding algorithm. However, according to [2] scoreboarding
> is a dynamic scheduling algorithm with out-of-order execution like the
> Tomasulo algorithm. Therefore, I have the following two questions:
>
> (1) Why is the minor CPU called an in-order CPU model if it has
> scoreboarding capabilities? Is it because the issuing happens in-order,
> nevertheless?
>
> (2) What is the difference between the O3 CPU model and the minor CPU
> model if the minor CPU already has scoreboarding? Does the O3 CPU offers a
> more sophisticated dynamic scheduling approach since [3] mentions register
> renaming (as in the Tomasulo algorithm).
>
> Many regards and many thanks in advance
>
> Felix Böseler
>
> [1] https://www.gem5.org/documentation/general_docs/cpu_models/minor_cpu
>
> [2] Hennessy, John L.; Patterson, David A. (op. 2012): Computer
> architecture. A quantitative approach. 5th ed. Waltham, MA: Morgan
> Kaufmann/Elsevier.
>
> [3] https://www.gem5.org/documentation/general_docs/cpu_models/O3CPU
> ___
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[gem5-users] Re: Compiling gem5 on ARM Based Host

2022-01-07 Thread Jason Lowe-Power via gem5-users
Hi Sam,

I was wondering when this problem would come up again. Here's a Jira issue
to track the same thing in a different context:
https://gem5.atlassian.net/browse/GEM5-1003

Could you do something like `du -h build/ | sort -h` to see what objects
are the biggest? I'm going to guess that there are ~100+ .o files that are
more than 20MB. At least, that was the case with RISC-V when I ran into
this problem.

We never did figure out why so many files were so big. The hypothesis was
something to do with pybind, but no one was able to provide solid evidence
of this. We did find that using a different compiler version, having
different libraries installed on the system, and removing unnecessary
includes seemed to make a difference, though. You may be able to use this
to at least work around the problem.

Here's the changeset that fixed it for RISC-V. However, I doubt it's going
to fix it again in your case.
https://gem5-review.googlesource.com/c/public/gem5/+/46820

You can also try this abandoned change, though it probably won't apply
cleanly or straightforwardly:
https://gem5-review.googlesource.com/c/public/gem5/+/46380

Cheers,
Jason

On Fri, Jan 7, 2022 at 9:39 AM Samuel Thomas via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I typically work on an x86 machine, but I’m trying to submit gem5 jobs to
> a cluster that runs ARM based hosts. Each source script compiles, I run
> into the following error when linking:
>
> /tmp/gem5.fast.unstripped.PI0JsN.ltrans45.ltrans.o: in function
> `ArmV8KvmCPU::updateThreadContext()':
> :(.text+0x25884): relocation truncated to fit:
> R_AARCH64_ADR_PREL_PG_HI21 against `.rodata’collect2: error: ld returned 1
> exit status
>
> It makes sense that the .text segment of the binary will be very large,
> and I see that there is a note on gem5’s architecture support documentation
> that it is out dated. I assume that I can try disassembling the binary and
> seeing if there is an alternative command to avoid this particular linker
> error, but I figured I would also ping the mailing list to see if there is
> an easier fix as well.
>
> Thank you all for your help!
>
> Best,
> Sam
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[gem5-users] Re: some problem about IO device's write or read function's return tick

2021-12-27 Thread Jason Lowe-Power via gem5-users
Hello,

If you are using *atomic* memory mode, then the tick number is mostly
ignored. If you're using *timing* mode, then the tick number should be used
by whatever object calls the read/write function and the delay is inserted
there. Also, if your program doesn't have a direct dependence on the I/O
device, the latency may be hidden. Enabling various debug flags should help
you track this down.

Cheers,
Jason

On Thu, Dec 23, 2021 at 8:58 AM lin via gem5-users 
wrote:

> Hi
>
> I make an IO device link to the membus and complete the Tick
> read(PacketPtr pkt) and the write() function .But I find that no matter how
> many ticks ( the funciton return n*tick) I set,the simSeconds no change.If
> it normal?If not , what can I do to set the return ticks of the read() or
> write() function?
>
> Thanks everyone!
>
>
>
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[gem5-users] Re: RISCV Full System with Ruby

2021-12-27 Thread Jason Lowe-Power via gem5-users
Hi Fu,

You can modify that file to import a Ruby-based cache hierarchy (e.g.,
MESI_Two_Level and MI_Example have been tested). Or, better yet, create
your own run script. `riscv_fs.py` is just an *example* of how to use the
standard library components.

Cheers,
Jason

On Fri, Dec 24, 2021 at 7:57 AM FU zx via gem5-users 
wrote:

> Hello!
>
>
> I just tried your riscv_fs.py in configs/example/gem5_library(I think this
> is where it is in the latest version, am I right?), and it did boot Linux,
> but I can't find how to config the script to enable the ruby cache system,
> the default config is just a classic cache model. Is there any guide to
> enable the ruby cache system in fs mode? Any help would be appreciated.
>
>
>
> Thanks in advance.
>
> Fu
>
>
>
>
>
>
>
>
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[gem5-users] Re: Adding use of an external library

2021-12-20 Thread Jason Lowe-Power via gem5-users
Hi Elliot,

You may be able to get some inspiration from the code in gem5/ext/*. This
is where we have included external libraries.

Cheers,
Jason

On Fri, Dec 17, 2021 at 6:21 PM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

>
> I have an external library that I would like to link with my gem5 build.
> How
> do I do that?  Also the code I want to compile that will use that library
> needs to include a particular .h file.  How do I work that into the build
> process?
>
> Thanks for tips on how to do this!  Regards - Eliot Moss
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[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

2021-12-16 Thread Jason Lowe-Power via gem5-users
Hi Brian,

You can try the patch linked below if you want x86 + multicore + classic.
There is a download button on that page. However, this isn't "officially"
supported.

Some Ruby protocols have been tested with x86 and multiple cores. The
details on the gem5-resources website and/or repo should describe what's
been tested.

Cheers,
Jason

On Thu, Dec 16, 2021 at 10:36 AM Brian Schwedock via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
> Thanks for the response.
>
> I will give full system mode a try. Will x86 + classic cache + multicore
> work with full system mode? Or do I also need to use, e.g., ruby caches?
>
> Thanks,
> Brian
>
> On Thu, Dec 16, 2021 at 9:23 AM Jason Lowe-Power 
> wrote:
>
>> Hi Brian,
>>
>> A few quick thoughts:
>> 1. x86 + classic cache + multicore is not supported. There is a changeset
>> on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303)
>> which may fix this, but it has not been tested widely.
>> 2. SE mode + pthreads will likely not work in all circumstances. The
>> system calls required for pthreads are complex and we may not have
>> implemented them to perfectly match their behavior on Linux
>> 3. Which leads to this: If you want to investigate multicore performance,
>> I would strongly suggest using full system mode. With gem5-resources (
>> https://resources.gem5.org/) it should be straightforward to set up. See
>> also the new gem5 standard library coming in gem5-21.2 (released next week)
>> as well.
>>
>> Cheers,
>> Jason
>>
>> On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,
>>>
>>> I'm trying to run a simple multithreaded C++ application in SE mode, but
>>> I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU
>>> does not deadlock. I'm running on the develop branch without modification.
>>>
>>> Here is the configuration I'm running:
>>> ./build/X86/gem5.opt configs/example/se.py
>>> --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache 
>>> --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8
>>>
>>> My application spawns 16 pthreads, and the threads perform atomic
>>> arithmetic operations and use pthread barriers. From what I can tell, the
>>> issue is that on one of the barriers only one or two threads are ever woken
>>> up once all threads are ready.
>>>
>>> When running with the above configuration, the simulation just hangs.
>>> When I run with ruby caches, the simulation eventually terminates from the
>>> Sequencer panicking on "Possible Deadlock detected."
>>>
>>> Are pthread barriers not currently supported? I tried using m5threads,
>>> but as per this issue (https://github.com/gem5/m5threads/issues/2), I
>>> can't compile it with my gcc and kernel versions.
>>>
>>> I would greatly appreciate any help with this issue.
>>>
>>> Thanks,
>>> Brian
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[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

2021-12-16 Thread Jason Lowe-Power via gem5-users
Hi Brian,

A few quick thoughts:
1. x86 + classic cache + multicore is not supported. There is a changeset
on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303)
which may fix this, but it has not been tested widely.
2. SE mode + pthreads will likely not work in all circumstances. The system
calls required for pthreads are complex and we may not have implemented
them to perfectly match their behavior on Linux
3. Which leads to this: If you want to investigate multicore performance, I
would strongly suggest using full system mode. With gem5-resources (
https://resources.gem5.org/) it should be straightforward to set up. See
also the new gem5 standard library coming in gem5-21.2 (released next week)
as well.

Cheers,
Jason

On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I'm trying to run a simple multithreaded C++ application in SE mode, but I
> seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU
> does not deadlock. I'm running on the develop branch without modification.
>
> Here is the configuration I'm running:
> ./build/X86/gem5.opt configs/example/se.py
> --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache 
> --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8
>
> My application spawns 16 pthreads, and the threads perform atomic
> arithmetic operations and use pthread barriers. From what I can tell, the
> issue is that on one of the barriers only one or two threads are ever woken
> up once all threads are ready.
>
> When running with the above configuration, the simulation just hangs. When
> I run with ruby caches, the simulation eventually terminates from the
> Sequencer panicking on "Possible Deadlock detected."
>
> Are pthread barriers not currently supported? I tried using m5threads, but
> as per this issue (https://github.com/gem5/m5threads/issues/2), I can't
> compile it with my gcc and kernel versions.
>
> I would greatly appreciate any help with this issue.
>
> Thanks,
> Brian
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[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

2021-12-08 Thread Jason Lowe-Power via gem5-users
You can call cpu.scheduleInstStop(, , )

So, you can set an initial instruction limit which will exit from the
simulate() call. Then, you can reset the stats and set a new instruction
limit with scheduleInstStop. Then, call simulate() again. When this second
simulate returns you can dump the stats.

You may or may not be able to do all this from se/fs.py, but it's pretty
straightforward to write your own gem5 runscript.

Cheers,
Jason

On Mon, Dec 6, 2021 at 6:41 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hi Prof. Jason,
>
> Thanks a lot for your response.
>
> The problem is not that we need to set one instruction limit but set one
> instruction limit, then reset the stats, and then terminate the simulation
> completely after the "total instruction limit". So, these are basically two
> termination points; one for warmup and the other for the actual simulation.
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
>
>
> On Mon, Dec 6, 2021 at 8:57 AM Jason Lowe-Power 
> wrote:
>
>> Hi Abdelrahman,
>>
>> I think you have the right approach. Is the simulation not exiting after
>> the warmup_inst instructions?
>>
>> Cheers,
>> Jason
>>
>> On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hello,
>>>
>>> I am trying to warm up my gem5 in order to train cache prediction. I am
>>> doing this by running a timed simulation in order to limit the number of
>>> instructions executed (if there is a more direction, that would be
>>> certainly welcomed).
>>>
>>> So, how to do this?
>>>
>>> I tried the following:
>>>
>>> system.setMemCtrl(valid_mem_ctls[args.memory_ctl])
>>> system.cpu.max_insts_any_thread = warmup_inst
>>>
>>> Also, I tried to set the duration desired for the simulation by passing
>>> it as an argument to the m5.simulate().
>>>
>>> Thanks.
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
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[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

2021-12-06 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman,

I think you have the right approach. Is the simulation not exiting after
the warmup_inst instructions?

Cheers,
Jason

On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to warm up my gem5 in order to train cache prediction. I am
> doing this by running a timed simulation in order to limit the number of
> instructions executed (if there is a more direction, that would be
> certainly welcomed).
>
> So, how to do this?
>
> I tried the following:
>
> system.setMemCtrl(valid_mem_ctls[args.memory_ctl])
> system.cpu.max_insts_any_thread = warmup_inst
>
> Also, I tried to set the duration desired for the simulation by passing it
> as an argument to the m5.simulate().
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
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[gem5-users] Re: fatal when adding a new CPU

2021-11-03 Thread Jason Lowe-Power via gem5-users
Hi Fengze,

Yeah, there's a lot of complicated and undocumented things you need to do
when initializing a CPU.

Here's a couple of pointers that may help. However, this code was written a
few years ago and is almost 4000 commits behind, so things have probably
changed since then!
Code: https://github.com/darchr/gem5/tree/simple-cpu/src/learning_gem5/part4
Notes:
https://github.com/darchr/gem5/blob/simple-cpu/src/learning_gem5/part4/notes.rst

I am certain that workload stuff has changed since I wrote the above code.
Though, I hope that it can help you get started.

Cheers,
Jason

On Wed, Nov 3, 2021 at 3:19 AM Fengze Yu via gem5-users 
wrote:

> Hi
>
> I was trying to add a new CPU inherit from BaseCPU:
>
> class MY_CPU: public BaseCPU
> {
> public:
>
> MY_CPU(const MY_CPUParams& p);
> ~MY_CPU(){}
> ...
> private:
> ...
> }
>
> but incurs the following running error: fatal: Process system.cpu.workload
> is not associated with any HW contexts!
>
> ...
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
> build/RISCV/mem/mem_interface.cc:793: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)
> build/RISCV/base/statistics.hh:277: warn: One of the stats is a legacy
> stat. Legacy stat is a stat that does not belong to any statistics::Group.
> Legacy stat is deprecated.
> build/RISCV/arch/riscv/linux/se_workload.cc:60: warn: Unknown operating
> system; assuming Linux.
> build/RISCV/sim/process.cc:290: fatal: Process system.cpu.workload is not
> associated with any HW contexts!
> ...
>
> Did I miss anything essential when creating a new CPU class?
>
>
> Thanks in advance
>
> Fengze
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[gem5-users] Re: RISCV Full System with Ruby

2021-11-02 Thread Jason Lowe-Power via gem5-users
Hello,

Yes. MI_example and MESI_Two_Level have been tested with the RISC-V board
in the components library. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/components-library/riscv_fs.py

I am working on the CHI protocol. I have a WIP changeset that I could
share. The final part I'm working on is getting DMA. That said, since
MI_example and MESI_Two_Level work, there's evidence that any protocol
should work.

Cheers,
Jason

On Tue, Nov 2, 2021 at 3:29 AM Javier Garcia Hernandez via gem5-users <
gem5-users@gem5.org> wrote:

> Hello.
>
> Is Ruby supported on RISCV FS?
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[gem5-users] Re: m5 pesudo

2021-11-01 Thread Jason Lowe-Power via gem5-users
Hello,

The m5 magic operations (either via magic instructions or addresses) will
work with all CPU models.

Cheers,
Jason

On Sat, Oct 30, 2021 at 8:31 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  Does “m5 --addr 0x1001 exit” take effect in the O3 system?
>
>
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[gem5-users] Re: Vector Instructions Support

2021-10-29 Thread Jason Lowe-Power via gem5-users
Hi Nitesh,

I don't think there's any good documentation. This may help with Arm SVE
support, but it's from a while ago. Things have changed since 2018.
https://community.arm.com/arm-research/b/articles/posts/simulating-the-arm-sve-with-gem5

On Fri, Oct 29, 2021 at 2:27 AM Nitesh Narayana GS 
wrote:

> Hi
>
> Thanks for the information. I will check the code base for that. Do you
> have any suggestions for the documentation regarding it ?
>
>
> Regards
> Nitesh
>
> On Thu, 28 Oct 2021 at 17:53, Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> For Arm, gem5 has SVE support and (some/most/all?) of the NEON
>> instructions. For x86, we support most 128-bit SIMD instructions, but very
>> few or no 256-bit or 512-bit SIMD instructions. I have heard of
>> forks/groups that have implemented many of the x86 vector instructions, and
>> I have heard that RISC-V vector extensions have been implemented. However,
>> these implementations have not been made public or have not been pushed
>> upstream.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Oct 28, 2021 at 4:08 AM nitesh--- via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi
>>>
>>> I am working on understanding VPUs and vector instructions, and am a bit
>>> new to the gem5 environment. I aI wanted to know if there is any official
>>> update on the vector instruction support for gem5 x86 and ARM? I see there
>>> are some forked versions available in the community but I am skeptical
>>> about their stability and version. Would like to know if anyone recommends
>>> any such version.
>>>
>>> I also see In this link
>>> https://www.gem5.org/documentation/general_docs/architecture_support/
>>> that gem5 has support for SSE in x86 but see little documentation regarding
>>> that. Also no mention of ARM vector instruction support.
>>>
>>> Sorry if I am wrong regarding the things I have mentioned.
>>>
>>> So any guidance, help, or advice regarding this will be great!!
>>>
>>> Thanks
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>>
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[gem5-users] Re: Vector Instructions Support

2021-10-28 Thread Jason Lowe-Power via gem5-users
Hello,

For Arm, gem5 has SVE support and (some/most/all?) of the NEON
instructions. For x86, we support most 128-bit SIMD instructions, but very
few or no 256-bit or 512-bit SIMD instructions. I have heard of
forks/groups that have implemented many of the x86 vector instructions, and
I have heard that RISC-V vector extensions have been implemented. However,
these implementations have not been made public or have not been pushed
upstream.

Cheers,
Jason

On Thu, Oct 28, 2021 at 4:08 AM nitesh--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi
>
> I am working on understanding VPUs and vector instructions, and am a bit
> new to the gem5 environment. I aI wanted to know if there is any official
> update on the vector instruction support for gem5 x86 and ARM? I see there
> are some forked versions available in the community but I am skeptical
> about their stability and version. Would like to know if anyone recommends
> any such version.
>
> I also see In this link
> https://www.gem5.org/documentation/general_docs/architecture_support/
> that gem5 has support for SSE in x86 but see little documentation regarding
> that. Also no mention of ARM vector instruction support.
>
> Sorry if I am wrong regarding the things I have mentioned.
>
> So any guidance, help, or advice regarding this will be great!!
>
> Thanks
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[gem5-users] Re: How to map elf section to physical memory

2021-10-26 Thread Jason Lowe-Power via gem5-users
Hi Jose,

This is an interesting question! My quick suggestion would be to "hack" the
loader/page table to skip the mapping portion when loading the elf section.

I don't fully understand exactly what the underlying "problem" is. That
said, we may be able to solve it "correctly" by generally skipping the
mapping during the elf loading if it's already been manually mapped by the
process.map function. This may be useful to upstream if this idea works.

Cheers,
Jason

On Fri, Oct 22, 2021 at 4:30 PM Monsalve, Jose Manuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
>
>
>
> I am working on developing the simulation of a system that contains two
> different regions of memory. One that maps to the cachable system memory
> (including cache hierarchy) but another region that is non-cachable, and
> which goes to a different memory (similar to scratchpad memory for the sake
> of this question). Additionally, in the executing code, I am trying to
> allocate some objects into this scratchpad memory address space from a
> section in the elf file. While running in SE mode. So, for example:
>
>
>
> System Memory address range -> 0x-0 to 0x00FFF
>
> Scratchpad memory address range -> 0x01000 to 0xF
>
>
>
> And in the linker script I place some sections in this region like:
>
>
>
> . = 0x1000
>
> .scratchpad {
>
>/* all symbols */
>
> }
>
>
>
> Then to use the __attribute__((section(“.scratchpad”)) in a given
> definition.
>
>
>
> However, when the loader loads this elf file, the virtual memory is
> assigned correctly, but it is mapped to another physical memory range that
> is different to the physical memory of the SPmem device.
>
>
>
> I know I can use the *.map()* method in the process like this (in python)
>
>
>
> process.map(Addr(args.mem_size),
>
> Addr(args.mem_size),
>
> SPMemorySize,
>
> False)
>
>
>
> This will only work if I don’t use sections in the linker script, and
> instead, manually assign the value of a pointer. (e.g. int **a = (int**)
> 0x1000;)
>
>
>
> But when I run it with the elf sections I get the error:
>
> build/RISCV/mem/page_table.cc:60: panic: panic condition !clobber
> occurred: EmulationPageTable::allocate: addr 0xc000 already mapped
>
>
>
> Because by the moment I reach the second map, the loader has already
> mapped the region before.
>
>
>
> I would appreciate if someone can share nay pointers on how to properly do
> this mapping between virt and physical.
>
>
>
> Thanks!
>
>
>
> Jose M Monsalve Diaz
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[gem5-users] Re: L2 or L3 cache interface

2021-10-25 Thread Jason Lowe-Power via gem5-users
Hi Fengze,

No, there is no defined interface between different levels of the cache in
Ruby. Ruby is a "black box" in some sense, with input on the CPU side and
output on the memory side. See
https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and
https://www.youtube.com/watch?v=XTIrVBb86aM_channel=JasonLowe-Power for
more information.

Cheers,
Jason

On Mon, Oct 25, 2021 at 6:18 AM Fengze Yu via gem5-users <
gem5-users@gem5.org> wrote:

>
> Hi
>
> What is the interface between L1 and L2 cache in Ruby cache coherence
> model? Is there a clear defined interface, similar to the icachePort and
> dcachePort between CPU and memory, between different levels of caches in
> Ruby?
>
>
> Thanks in advance
>
> Fengze Yu
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[gem5-users] Re: Use xbar stat in BaseCPU

2021-10-22 Thread Jason Lowe-Power via gem5-users
Hi Victor,

It's not super easy to access stats between SimObjects. I would suggest
computing any and all formulas after running the simulation, not during the
simulation loop.

You can either parse the stats.txt or use the new python stats interface (
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/python/m5/stats/gem5stats.py#237)
to access stats from your python run script.

Cheers,
Jason

On Thu, Oct 21, 2021 at 4:12 PM Victor Kariofillis via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I have created a new stat of type Formula in the xbar.cc/hh files. There
> I aggregate all the different transDist types. I'd like to use this newly
> created stat to compute another stat in the BaseCPU object. What is the
> best way to have access to it (i.e., allTransactions stat) from BaseCPU? Is
> there any way to make it globally accessible?
>
> Thanks
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[gem5-users] Re: SPEC 2017 Benchmarks: Input Files Not Found

2021-10-18 Thread Jason Lowe-Power via gem5-users
Hi Reiko,

I would guess that it's a permission issue as well. Maybe, by default, when
booting the image it logs in as a regular user?

What I would do is not pass the rcS script and log in interactively with
the m5term (see util/term). Then, run the commands in the rcS file one at a
time manually to see what's going on.

Cheers,
Jason

On Sat, Oct 16, 2021 at 4:34 PM Reiko Matsuda-dunn via gem5-users <
gem5-users@gem5.org> wrote:

> Hello!
>
> I am trying to run the SPEC 2017 benchmarks with gem5 and have had luck
> with some of them, but many are unable to find their input files. If I
> mount the disk image I'm using, I can actually run these benchmarks
> directly on the disk image as root (they can open their input files).
> However, if I have the exact same command in a .rCs file passed as a script
> to $build/ARM/gem5.opt configs/fs.py, I get these file not found errors.
>
> I'm checking all my paths, but I'm skeptical that that is the issue, as
> some benchmarks consistently run and other specific benchmarks do not.
>
> An example of the full command I'm running is:
>
> $build/ARM/gem5.opt --outdir=run/exchange2_s configs/fs_ARM.py
> --checkpoint-dir=checkpoint/exchange2_s -r 1
> --disk-image=../m5_binaries/disks/gem5.img
> --kernel=../m5_binaries/binaries/vmlinux.arm64
> --script=scripts/exchange2_s.rcS --mem-size=4GB --cpu-type=AtomicSimpleCPU
> --caches --l2cache --l1d_size=32kB --l1i_size=32kB --l2_size=512kB
> --checkpoint-at-end --maxinsts=20
>
> The benchmarks with these errors include: cam4_s, exchange2_s, fotonik_s,
> nab_s, omnetpp_s, pop2_s, roms_s, wrf_s, and x264_s.
>
> Could this possibly be a permissions issue? The input files in question
> have -rw-rw-r-- as their permissions, which seems to me like it should be
> okay.
>
> Any ideas would be appreciated!
> Thanks,
> Reiko
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[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

2021-10-12 Thread Jason Lowe-Power via gem5-users
I would suggest using DPRINTF instead of cout. It's possible that some
print statements aren't being flushed.

Jason

On Mon, Oct 11, 2021 at 7:16 AM Sampad Mohapatra  wrote:

> Hi Jason,
>
> I have added a std::cout statement to the resetstats()'s body and I am
> calling m5_reset_stats from my GPU benchmarks.
> The GPU kernels are launched right after reset is called. I pipe the
> output of simulations to a file. But, strangely enough
> some outputs show the std::cout statements while others don't. What could
> be the reason ?
>
> Thanks,
> Sampad
>
> On Mon, Oct 4, 2021 at 12:08 PM Jason Lowe-Power 
> wrote:
>
>> Hi Sampad,
>>
>> Here is where m5_reset_stats is implemented in the simulator:
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303
>>
>> There are a large number of steps between when the guest code calls
>> m5_reset_stats and when the above function executes, but this should help
>> you start hacking :).
>>
>> Cheers,
>> Jason
>>
>> On Sat, Oct 2, 2021 at 4:05 AM Sampad Mohapatra via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi All,
>>>
>>> I need to set a bool variable in src/cpu/simple/base.(hh|cc) to be true
>>> when m5_reset_stats() is *explicitly *called from some binary executing
>>> on gem5. Using this bool and instruction count, I want to exit the
>>> simulation.
>>>
>>> How can I modify the body (hack) of m5_reset_stats() to call other
>>> functions ? Where is its body defined ?
>>> If not possible, then is there any alternative way to set the bool
>>> variable when m5_reset_stats() is *explicitly* called ?
>>>
>>> Thank You,
>>> Sampad Mohapatra
>>>
>>>
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>>
>>
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[gem5-users] Re: Seg. Fault while "Creating a simple configuration script"

2021-10-08 Thread Jason Lowe-Power via gem5-users
Hello,

Does the file configs/learning_gem5/part1/simple.py work for you? If so,
then there is probably a small mistake in your configuration script. If
this is the case, can you send your script (maybe off list)? I would like
to understand the problem and improve the error message.

Cheers,
Jason

On Fri, Oct 8, 2021 at 12:35 AM saheed - via gem5-users 
wrote:

> Hello,
>
> I am following the Getting started instructions, I am stuck at the
> beginning!
> "Creating a simple configuration script".
>
> I am using the current stable version of gem5 on a Debian (buster) system.
>
> 1. `build/X86/mem/mem_interface.cc:793: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)`
>
>  I managed to fix this by increasing `system.mem_ranges` to 8GB.
> Buried somewhere on the internet is a comment about something defaulting to
> 8GB.
>
> 2. `warn: No dot file generated. Please install pydot to generate the dot
> file and pdf.`
>
>   I have installed this with `sudo apt install python-pydot
> python-pydot-ng graphviz` . Could this be because my system is running in
> server mode (no GUI)?
>
> 3. *The SEG. FAULT:*
> Here is the whole load down, please let me know what I am doing wrong
>
> ~/DEV/comp-arch/gem5$ build/X86/gem5.opt configs/tutorial/simple.py
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.1.0.2
> gem5 compiled Oct  8 2021 08:16:42
> gem5 started Oct  8 2021 09:27:49
> gem5 executing on saheed-deb, pid 22197
> command line: build/X86/gem5.opt configs/tutorial/simple.py
>
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
> Beginning simulation!
> build/X86/sim/simulate.cc:107: info: Entering event queue @ 0.  Starting
> simulation...
> gem5 has encountered a segmentation fault!
>
> --- BEGIN LIBC BACKTRACE ---
> build/X86/gem5.opt(+0x9275b9)[0x55a3a34815b9]
> build/X86/gem5.opt(+0x9417ff)[0x55a3a349b7ff]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12730)[0x7f63c4fbf730]
> build/X86/gem5.opt(+0x986654)[0x55a3a34e0654]
> build/X86/gem5.opt(+0x4b9847)[0x55a3a3013847]
> build/X86/gem5.opt(+0x4b21a5)[0x55a3a300c1a5]
> build/X86/gem5.opt(+0x4b2e18)[0x55a3a300ce18]
> build/X86/gem5.opt(+0x933e75)[0x55a3a348de75]
> build/X86/gem5.opt(+0x95aad1)[0x55a3a34b4ad1]
> build/X86/gem5.opt(+0x95b2a2)[0x55a3a34b52a2]
> build/X86/gem5.opt(+0xe7d3ce)[0x55a3a39d73ce]
> build/X86/gem5.opt(+0x39276d)[0x55a3a2eec76d]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyCFunction_Call+0xfb)[0x7f63c5243b5b]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x78e0)[0x7f63c5044700]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyFunction_FastCallKeywords+0x93)[0x7f63c5243123]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x7b95)[0x7f63c50449b5]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f63c516c46e]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCode+0x1b)[0x7f63c516d23b]
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(+0x1a2bdd)[0x7f63c5170bdd]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyMethodDef_RawFastCallKeywords+0x2a5)[0x7f63c5242c75]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyCFunction_FastCallKeywords+0x25)[0x7f63c5243a05]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x8bde)[0x7f63c50459fe]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyFunction_FastCallKeywords+0x93)[0x7f63c5243123]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x7b95)[0x7f63c50449b5]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f63c516c46e]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCode+0x1b)[0x7f63c516d23b]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyRun_StringFlags+0x8b)[0x7f63c513afeb]
> build/X86/gem5.opt(+0x93fa1f)[0x55a3a3499a1f]
> --- END LIBC BACKTRACE ---
> Segmentation fault
>
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[gem5-users] Re: Porting a configuration file from gem5 v20 to gem5 v21

2021-10-06 Thread Jason Lowe-Power via gem5-users
Hi Ali,

Is your guest code 32-bit Arm? If so, I think this could be the problem in
SE mode: https://gem5.atlassian.net/browse/GEM5-1074

Cheers,
Jason

On Tue, Oct 5, 2021 at 7:45 AM Ali Ghandour via gem5-users <
gem5-users@gem5.org> wrote:

> In FS mode, full errror stack below:
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/ARM/python/m5/main.py", line 455, in main
>   File "./RPIv4.py", line 535, in 
> main()
>   File "./RPIv4.py", line 512, in main
> root.system = systemCreate(args)
>   File "./RPIv4.py", line 297, in systemCreate
> system = RPISystemCreate(ArmSystem, args, mode)
>   File "./RPIv4.py", line 182, in RPISystemCreate
> return RPISystem(args, mode)
>   File "./RPIv4.py", line 127, in __init__
> self.configMem(args)
>   File "./RPIv4.py", line 158, in configMem
> self.cpu_cluster.connectDirect(self.membus)
>   File
> "/home/ali/Desktop/spirals/reproduce-spectre-gem5/gem5/./ARMv8A_Cortex_A72.py",
> line 325, in connectDirect
> cpu.dtb.walker.port = bus.slave
>   File "build/ARM/python/m5/SimObject.py", line 1416, in __getattr__
> AttributeError: object 'ARM_A72_TLB_L1D' has no attribute 'walker'
>   (C++ object is not yet constructed, so wrapped C++ methods are
> unavailable.)
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[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

2021-10-04 Thread Jason Lowe-Power via gem5-users
Hi Sampad,

Here is where m5_reset_stats is implemented in the simulator:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303

There are a large number of steps between when the guest code calls
m5_reset_stats and when the above function executes, but this should help
you start hacking :).

Cheers,
Jason

On Sat, Oct 2, 2021 at 4:05 AM Sampad Mohapatra via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> I need to set a bool variable in src/cpu/simple/base.(hh|cc) to be true
> when m5_reset_stats() is *explicitly *called from some binary executing
> on gem5. Using this bool and instruction count, I want to exit the
> simulation.
>
> How can I modify the body (hack) of m5_reset_stats() to call other
> functions ? Where is its body defined ?
> If not possible, then is there any alternative way to set the bool
> variable when m5_reset_stats() is *explicitly* called ?
>
> Thank You,
> Sampad Mohapatra
>
>
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[gem5-users] Re: Get Size of Stack and Heap

2021-09-30 Thread Jason Lowe-Power via gem5-users
Hi Ange,

If you're using SE mode, you may be able to augment the allocation code to
track the heap size. E.g.,
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/mem_state.cc#108

In fact, the MemState object tracks both the stack and the heap, so you can
get a lot of information from that. Again, this assumes you're using SE
mode.

If you're using FS mode, it will be a bit more complicated. You're on the
right track with the readArchInReg. I'm not sure exactly how Arm tracks the
heap, but I would dig into the remote GDB implementation to see if there
are any hints in that code.

Cheers,
Jason

On Thu, Sep 23, 2021 at 9:46 AM Ange via gem5-users 
wrote:

> Hi all,
>
> I am trying to keep track of the size of the stack and heap while
> executing a binary, and at the moment, I can get the address of the stack
> pointer using this line of code
> cpu->readArchIntReg(ArmISA::INTREG_SP ,tid).
> I am also trying to read the frame pointer (FP), but I am having trouble
> getting the address for it
> because it always prints zero as its address, and I am using Register 11
> for the FP (cpu->readArchIntReg(ArmISA::INTREG_R11) ).
> Am I doing something wrong, or is there a better way to get the stack
> size?  and also the heap size with its addresses?
>
> I saw that someone asked a similar question a while back on this forum,
> but it was not fully answered.
> Here is the link
> https://www.mail-archive.com/gem5-users@gem5.org/msg04154.html
>
> I need help!
>
> Ange
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[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
Yeah. I would suggest working on a native linux machine if you're going to
use KVM. If you're not using KVM, then WSL *should* (no promises ;)) work
OK.

Cheers,
Jason

On Thu, Sep 23, 2021 at 3:21 PM Reiko Matsuda-dunn <
reiko.matsudad...@colorado.edu> wrote:

> Thanks for the resources! Seems like quite a can of worms.It's almost
> looking like it could be easier to partition a computer for Linux and start
> over. Would you recommend that as an alternative?
>
> All th
>
> On Thu, Sep 23, 2021 at 1:36 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi Reiko,
>>
>> The KVM CPU requires that the host platform supports KVM. Given that
>> you're using WSL, this means that you need to have nested virtualization
>> enabled and implemented on your WSL kernel.
>> https://www.reddit.com/r/bashonubuntuonwindows/comments/ldbyxa/what_is_the_current_state_of_kvm_acceleration_on/
>> has more information.
>>
>> We can try to help you with this, but currently we only support KVM on
>> native Linux hosts.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Sep 23, 2021 at 11:36 AM Reiko Matsuda-dunn via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hello,
>>>
>>> I'm trying to troubleshoot this error (output below).  I've looked at
>>> prior posts in this mailing list and was able to change perf_event_paranoid
>>> to -1 ( I confirmed this with $cat /proc/sys/kernel/perf_event_paranoid,
>>> which returns -1, although it resets to 2 every time I reboot). It looks
>>> like there's some mention of a patch, but I haven't been able to find that
>>> patch. If anyone could point me to that, or offer other suggestions I would
>>> be grateful!
>>>
>>> I'm using gem5 21, WSL2, and have otherwise follower the tutorial here:
>>> https://www.gem5.org/documentation/gem5art/tutorials/spec-tutorial
>>> <https://secure-web.cisco.com/17IBO0xQxkZZIebcGCBpl1G0BsdiJYaESwCqShOyCJRixJFvPEMpbaePLfLril03_Qv4GGBoSf1-s_RSxDFuTNEd3nZ6jb0A1cTSgSVFF0TlW1yWTMajw2VxDcgoQK9MBNdDMxXseHmenbOhFoHzv2_nSqldKvC5u8wj1QXxh6AWAgT-lqcyDlX3wNkRQ-RubhrlVql0h1nLr5X3xLcaS9VTm2VvIJRRkiCZ9AUQeNGn0Tw2BWM1jWjW9qSghZtSB-ir8AP83Di1pPW25Q2ALWnuR-YoVfQ9JL4eL6Aql49G8VUkDU4LtTjLHprwIYfe7xfz-J2mBNwAs6Cy_qgF8Z7M1c6GbEc_4GBF_QUvdVYZhz4L46EEpidbJb2txcdtl4NghPNs9ua1gBj5wynZ2j1GynRoxrrc_Y_sJnfR_xMQxGI9EcqCfe9zm2-St2Zq3clFno40v_7K-s8JTR5a8GA/https%3A%2F%2Fwww.gem5.org%2Fdocumentation%2Fgem5art%2Ftutorials%2Fspec-tutorial>
>>>
>>> My launch_spec2017_experiment.py has been modified slightly for the
>>> paths and gem5 version.
>>>
>>> Thanks for all your help,
>>> Reiko
>>>
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (128 Mbytes)
>>> build/X86/sim/kernel_workload.cc:46: info: kernel located at:
>>> vmlinux-4.19.83
>>> build/X86/dev/serial/terminal.cc:170: warn:
>>> Sockets disabled, not accepting terminal connections
>>> build/X86/base/remote_gdb.cc:377: warn:
>>> Sockets disabled, not accepting gdb connections
>>> build/X86/mem/coherent_xbar.cc:140: warn:
>>> CoherentXBar system.cpu.mmucache.mmubus has no snooping ports attached!
>>> build/X86/dev/intel_8254_timer.cc:125: warn:
>&g

[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Reiko,

The KVM CPU requires that the host platform supports KVM. Given that you're
using WSL, this means that you need to have nested virtualization enabled
and implemented on your WSL kernel.
https://www.reddit.com/r/bashonubuntuonwindows/comments/ldbyxa/what_is_the_current_state_of_kvm_acceleration_on/
has more information.

We can try to help you with this, but currently we only support KVM on
native Linux hosts.

Cheers,
Jason

On Thu, Sep 23, 2021 at 11:36 AM Reiko Matsuda-dunn via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I'm trying to troubleshoot this error (output below).  I've looked at
> prior posts in this mailing list and was able to change perf_event_paranoid
> to -1 ( I confirmed this with $cat /proc/sys/kernel/perf_event_paranoid,
> which returns -1, although it resets to 2 every time I reboot). It looks
> like there's some mention of a patch, but I haven't been able to find that
> patch. If anyone could point me to that, or offer other suggestions I would
> be grateful!
>
> I'm using gem5 21, WSL2, and have otherwise follower the tutorial here:
> https://www.gem5.org/documentation/gem5art/tutorials/spec-tutorial
> My launch_spec2017_experiment.py has been modified slightly for the paths
> and gem5 version.
>
> Thanks for all your help,
> Reiko
>
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (128 Mbytes)
> build/X86/sim/kernel_workload.cc:46: info: kernel located at:
> vmlinux-4.19.83
> build/X86/dev/serial/terminal.cc:170: warn:
> Sockets disabled, not accepting terminal connections
> build/X86/base/remote_gdb.cc:377: warn:
> Sockets disabled, not accepting gdb connections
> build/X86/mem/coherent_xbar.cc:140: warn:
> CoherentXBar system.cpu.mmucache.mmubus has no snooping ports attached!
> build/X86/dev/intel_8254_timer.cc:125: warn:
> Reading current count from inactive timer.
> build/X86/cpu/kvm/base.cc:152: info: KVM:
> Coalesced MMIO disabled by config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/cpu/kvm/base.cc:152: info: KVM:
> Coalesced MMIO disabled by config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/sim/simulate.cc:107: info:
> Entering event queue @ 0.  Starting simulation...
> build/X86/cpu/kvm/perfevent.cc:183: panic:
> PerfKvmCounter::attach failed (2)
> Memory Usage: 8738772 KBytes
> build/X86/cpu/kvm/perfevent.cc:183: panic:
> PerfKvmCounter::attach failed (2)
> Memory Usage: 8738772 KBytes
> Program aborted at tick 0
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[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Xihui,

The error is "died with "

I would guess you're out of memory or trying to compile too many files at
once. But, it could be many different problems. If it's an issue with
dependencies or your host, you can always use our docker images:
https://www.gem5.org/documentation/general_docs/building#:~:text=dev%20pkg-config-,Docker,-For%20users%20struggling

Cheers,
Jason

On Thu, Sep 23, 2021 at 1:01 AM Xihui Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
>   Thanks for your help.
>   But there are lots of errors in the first time to build gem5.
>
> scons: *** [build/X86/mem/ruby/protocol/DMA_Controller.py.cc]
> CalledProcessError : Command '['/home/xihui/下载/gem5/build/X86/marshal',
> 'build/X86/mem/ruby/protocol/DMA_Controller.py']' died with
> .
> Traceback (most recent call last):
>   File "/usr/lib/scons/SCons/Action.py", line 1209, in execute
> result = self.execfunction(target=target, source=rsources, env=env)
>   File "/home/xihui/下载/gem5/build/X86/SConscript", line 1293, in
> embedPyFile
> marshalled = subprocess.check_output(
>   File "/usr/lib/python3.8/subprocess.py", line 415, in check_output
> return run(*popenargs, stdout=PIPE, timeout=timeout, check=True,
>   File "/usr/lib/python3.8/subprocess.py", line 516, in run
> raise CalledProcessError(retcode, process.args,
> subprocess.CalledProcessError: Command
> '['/home/xihui/下载/gem5/build/X86/marshal',
> 'build/X86/mem/ruby/protocol/DMA_Controller.py']' died with
> .
> scons: building terminated because of errors.
>
> Do you have any opinion or suggestion?
>
>
> Regards,
> Xihui
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[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-20 Thread Jason Lowe-Power via gem5-users
Hi Xihui,

That's just a warning and you can safely ignore it. The most recent hotfix
release should remove this warning as well.

Cheers,
Jason

On Sun, Sep 19, 2021 at 10:02 PM Xihui Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone:
>
> I am a beginner with GEM5.
> There was a problem when I ran the project for the first time.
>
> Warning: Deprecated names are not supported by the compiler.
>
> I found no solution in the mailing list and website.
> Could you please give me any help to fix it?
>
> Thanks.
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[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Sam,

I would *guess* it's the draining code getting stuck in an infinite loop.
The draining code calls "drain" on all SimObjects in the system, and they
do their thing. Then, the drain code asks all SimObjects if they're done
draining. If not, it starts over and calls drain on all objects again. If
some object isn't draining properly or if there is some circular
dependence, there could be a "live lock" in this code. Just a guess, though.

Cheers,
Jason

On Wed, Sep 8, 2021 at 10:00 AM Thomas, Samuel 
wrote:

> Hi Jason,
>
> Thanks for your help. I think I've honed in on the source of the problem
> -- namely, number of cpus. Is there a reason why having multiple CPUs in a
> particular configuration would limit the simulator's ability to write a
> checkpoint?
>
> Again, thank you for your help!
>
> Best,
> Sam
>
> On Wed, Sep 8, 2021 at 11:12 AM Jason Lowe-Power 
> wrote:
>
>> Hi Sam,
>>
>> Sorry for the frustration. Writing better documentation is always #2 on
>> the priority list :(.
>>
>> I always tell people not to trust any of the "options" to fs.py and
>> se.py. Those scripts have gotten so far beyond "out of hand" at this point
>> that they are almost useless. They are trying to be everything to everyone,
>> and they end up just being a mess of spaghetti code and confusion.
>>
>> To take a checkpoint, you can add the following code to a python
>> runscript:
>>
>> m5.simulate(1)
>> m5.checkpoint()
>> m5.simulate(2)
>> m5.checkpoint()
>>
>> I tested the above code by adding it to the
>> configs/learning_gem5/part1/two_level.py file.
>>
>> *Maybe* this is what --take-checkpoints is doing. It's certainly what it
>> was *supposed* to do, but again, since this code has gotten so out of hand,
>> who knows if it's actually doing what it advertises.
>>
>> If you want to use the m5ops to checkpoint, the code would look
>> something like the following (this isn't tested and it's off the top of my
>> head).
>>
>> while 1:
>>   exit_event = m5.simulate()
>>   if exit_event.getCause() == 'checkpoint'):
>> m5.checkpoint(m5.outdir + '/' + str(num))
>>   else:
>> break
>>
>> To restore from a checkpoint, pass the checkpoint directory as the only
>> parameter to m5.instantiate(ckpt_dir=).
>>
>> Hope this helps! If you're still experiencing a hang in this case, it's
>> probably a bug in the drain() code somewhere. You can try to use one of the
>> drain debug flags (I don't know exactly what these are... check gem5
>> --debug-help for a list of debug flags). Making the python runscript do
>> exactly what you expect will also help with debugging. When you control the
>> script, adding prints is easy, too!
>>
>> Finally, the file src/python/m5/simulate.py may be helpful to figure out
>> what's going on when instantiating, simulating, checkpointing, etc.
>>
>> Cheers,
>> Jason
>>
>> On Wed, Sep 8, 2021 at 6:14 AM Thomas, Samuel via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi all,
>>>
>>> Just to follow up, because I can see that there have been some issues
>>> with not including all of the requisite issues in other threads, here is
>>> the full output from what I described above.
>>>
>>> gem5 Simulator System.  http://gem5.org
>>> gem5 is copyrighted software; use the --copyright option for details.
>>>
>>> gem5 version 21.1.0.0
>>> gem5 compiled Sep  7 2021 19:28:16
>>> gem5 started Sep  8 2021 09:09:11
>>> gem5 executing on sam-Precision-Tower-5810, pid 445665
>>> command line: build/X86/gem5.opt -d $CURR_DIR/debug
>>> $CURR_DIR/configs/example/fs.py --caches --l2cache --mem-type DDR3_1600_8x8
>>> --mem-size 2GB --meta-size 512kB --num-cpus 4 --disk-image $DISK_PATH
>>> --kernel $KERNEL_PATH --cpu-type $CPU_TYPE --script=$SCRIPT_PATH
>>> --l2_size=1MB --take-checkpoints=1,2
>>>
>>> warn: iobus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: bridge.master is deprecated. `master` is now called `mem_side_port`
>>> warn: membus.master is deprecated. `master` is now called
>>> `mem_side_ports`
>>> warn: bridge.slave is deprecated. `slave` is now called `cpu_side_port`
>>> warn: iobus.master is deprecated. `master` is now called `mem_side_ports`
>>> warn: apicbridge.slave is deprecated. `slave` is now called
>>> `cpu_side_port`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`

[gem5-users] Re: Is it ok to remove `maxRoutingTableSizeCheck`?

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Emil,

You can remove that check. However, you should note that the classic caches
aren't designed to support high-bandwidth operation. Also, this assert
triggering could be a sign that there's infinite queuing somewhere (which
is one reason why the classic caches aren't great for high bandwidth
systems).

Cheers,
Jason

On Wed, Sep 8, 2021 at 3:48 AM Emil VATAI via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> We are trying to do some simulations. We are using a simulator based on an
> old version of Gem5 ([1] created to simulate a64fx chip).
> We made some further modifications, namely replaced `SnoopMask` to be of
> type `std::bitset<>` to be able to run more-or-less arbitrary number of
> cores. And running with more cores resulted in triggering the following
> panic in `coherent_xbar.cc` (it occurs 2x in the code, around line 330 and
> 400 [3], not sure which one was triggered).
> ```
> panic_if(routeTo.size() > 512, "Routing table exceeds 512 packets\n");
> ```
> comparing this to a more recent version of gem5 the constant 512 seems to
> be the `maxRoutingTableSizeCheck` variable [4].
>
> My question is, how important is that check? How will it impact the
> simulation? Will it still be a "correct" simulation (or will skipping that
> check do something silly, like skip simulation half of the memory writes or
> something like that).
>
> Best,
> Emil
>
> [1] https://github.com/RIKEN-RCCS/riken_simulator
> [2] https://github.com/bgerofi/riken_simulator/
> [3]
> https://github.com/bgerofi/riken_simulator/blob/1f6627cf95688c508b73c8ead6838aa1f843f436/src/mem/coherent_xbar.cc#L339
> [4]
> https://github.com/gem5/gem5/blob/87c121fd954ea5a6e6b0760d693a2e744c2200de/src/mem/coherent_xbar.cc#L346
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[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Sam,

Sorry for the frustration. Writing better documentation is always #2 on the
priority list :(.

I always tell people not to trust any of the "options" to fs.py and se.py.
Those scripts have gotten so far beyond "out of hand" at this point that
they are almost useless. They are trying to be everything to everyone, and
they end up just being a mess of spaghetti code and confusion.

To take a checkpoint, you can add the following code to a python runscript:

m5.simulate(1)
m5.checkpoint()
m5.simulate(2)
m5.checkpoint()

I tested the above code by adding it to the
configs/learning_gem5/part1/two_level.py file.

*Maybe* this is what --take-checkpoints is doing. It's certainly what it
was *supposed* to do, but again, since this code has gotten so out of hand,
who knows if it's actually doing what it advertises.

If you want to use the m5ops to checkpoint, the code would look
something like the following (this isn't tested and it's off the top of my
head).

while 1:
  exit_event = m5.simulate()
  if exit_event.getCause() == 'checkpoint'):
m5.checkpoint(m5.outdir + '/' + str(num))
  else:
break

To restore from a checkpoint, pass the checkpoint directory as the only
parameter to m5.instantiate(ckpt_dir=).

Hope this helps! If you're still experiencing a hang in this case, it's
probably a bug in the drain() code somewhere. You can try to use one of the
drain debug flags (I don't know exactly what these are... check gem5
--debug-help for a list of debug flags). Making the python runscript do
exactly what you expect will also help with debugging. When you control the
script, adding prints is easy, too!

Finally, the file src/python/m5/simulate.py may be helpful to figure out
what's going on when instantiating, simulating, checkpointing, etc.

Cheers,
Jason

On Wed, Sep 8, 2021 at 6:14 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> Just to follow up, because I can see that there have been some issues with
> not including all of the requisite issues in other threads, here is the
> full output from what I described above.
>
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.1.0.0
> gem5 compiled Sep  7 2021 19:28:16
> gem5 started Sep  8 2021 09:09:11
> gem5 executing on sam-Precision-Tower-5810, pid 445665
> command line: build/X86/gem5.opt -d $CURR_DIR/debug
> $CURR_DIR/configs/example/fs.py --caches --l2cache --mem-type DDR3_1600_8x8
> --mem-size 2GB --meta-size 512kB --num-cpus 4 --disk-image $DISK_PATH
> --kernel $KERNEL_PATH --cpu-type $CPU_TYPE --script=$SCRIPT_PATH
> --l2_size=1MB --take-checkpoints=1,2
>
> warn: iobus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: bridge.master is deprecated. `master` is now called `mem_side_port`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: bridge.slave is deprecated. `slave` is now called `cpu_side_port`
> warn: iobus.master is deprecated. `master` is now called `mem_side_ports`
> warn: apicbridge.slave is deprecated. `slave` is now called `cpu_side_port`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: apicbridge.master is deprecated. `master` is now called
> `mem_side_port`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: iobus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave 

[gem5-users] Re: Query: Valgrind speed in FS

2021-09-07 Thread Jason Lowe-Power via gem5-users
Hi Sindhuja,

Yes, there is an expectation that valgrind causes a slowdown. Let me give
you a couple of suggestions.

1. Make sure you compile without tcmalloc (e.g., scons
build//gem5.opt --without-tcmalloc). Using tcmalloc will make
valgrind miss all allocations.
2. Use the suppressions file in util/valgrind-suppressions. This will hide
most of the python "errors". It was recently updated to suppress many more
errors that aren't really errors.

That said, I've had some recent problems myself with valgrind and the new
suppressions file being *very* slow. I think this is something we need to
look into. If you have any ideas on how to improve the performance, we
would appreciate hearing them! Otherwise, I guess we'll all just have to
keep waiting overnight ;)

Cheers,
Jason

On Tue, Sep 7, 2021 at 2:20 PM Sindhuja Gopalakrishnan Elango via
gem5-users  wrote:

> Hi Community,
>
> I ran into bad_alloc issues in GEM5 with the full system simulation of
> SPEC 2006 benchmarks.
>
> Suspecting a memory leak, I wanted to use valgrind to understand better.
>
>
>
> Without valgrind option, it takes less than 10 minutes for kernel to boot
> and also run the 400.perlbench/attrs benchmark.
>
> But with valgrind, it has crossed 2 hrs and the kernel hasn’t yet booted.
>
>
>
> Usage:
>
> valgrind --log-file=attrs.val.txt --error-limit=no   $GEM5_CMD
>
>
>
> I would like to know if this slowdown is reasonable with valgrind?
>
> And do you have any suggestions for a memory leak detection tool that is
> faster than valgrind and works well with gem5?
>
>
>
> Appreciate your time and effort. Thanks much.
>
>
>
> Best Regards
>
> Sindhuja
>
>
>
>
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[gem5-users] Re: regarding building of dependencies

2021-09-02 Thread Jason Lowe-Power via gem5-users
Hello,

It should be X86 (capitol X) instead of x86. You can see the files in
gem5/build_opts for the different possibilities for default build variables.

Cheers,
Jason

On Thu, Sep 2, 2021 at 3:58 AM Sravani Sravanam 20PHD7041 via gem5-users <
gem5-users@gem5.org> wrote:

>  sir,
> i am sravani sravanam a research scholar in vit ap university.while
> running at initial stage like
> scons build/x86/gem5.opt -j2 i am getting an error like this
> Error: Cannot find variables file
> /home/hp/Desktop/srav/gem5/build/variables/x86
>or default file(s) /home/hp/Desktop/srav/gem5/build_opts/x86.
> please help me
> thanking you
> sravani sravanam
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[gem5-users] Re: Collecting Two Sets of Data Within Same Simulation

2021-08-13 Thread Jason Lowe-Power via gem5-users
Hi Sam,

This is a use case that I don't think we've thought about in the mainline
gem5. I think the easiest solution would be to add some custom Statistics
objects to track the info from the function you're interested in.

Cheers,
Jason

On Wed, Aug 11, 2021 at 10:59 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I'm currently running a full system simulation, and would like to collect
> statistics from one particular function as well as overall statistics from
> the simulation. Unfortunately, the function gets called many times, so
> simply dumping stats at the beginning and end of the function makes the
> resulting stats file too large to do any analysis on.
>
> Is there an easy way to get around this issue?
>
> Thank you for your help!
>
> Best,
> Sam
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[gem5-users] Re: 答复: gem5 v21.1 released!

2021-07-29 Thread Jason Lowe-Power via gem5-users
Hi Liyichao,

We welcome contributions to the gem5 resources! Currently, we have full
system resources available for x86 and one available for RISC-V. We don't
have any Arm resources available right now, but that's only because we
haven't had the time (or resources ;)) to get around to it. Again, we
welcome contributions, though!

Cheers,
Jason

On Wed, Jul 28, 2021 at 6:24 PM Liyichao via gem5-users 
wrote:

> Hi Bruce:
>
>  I see the GEM5 resource mentioned on the GEM5 official website.
> Are all the resources provided in the GEM5 resource based on x86? For
> example, SPEC2017, are there AARCH64-based versions available for these
> resources?
>
>
>
> Best regards,
>
> Liyichao
>
>
>
>
>
> *发件人:* Bobby Bruce via gem5-users [mailto:gem5-users@gem5.org]
> *发送时间:* 2021年7月29日 8:51
> *收件人:* gem5 Developer List ; gem5 users mailing list <
> gem5-users@gem5.org>; gem5-annou...@gem5.org
> *抄送:* Bobby Bruce 
> *主题:* [gem5-users] gem5 v21.1 released!
>
>
>
> Dear all,
>
>
>
> gem5 v21.1.0.0 has officially been released.
>
>
>
> You can use  `git clone https://gem5.googlesource.com/public/gem5`
>  to obtain the latest release
> and consult the RELEASE-NOTES.md for a high-level overview of significant
> changes:
> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md
>
>
>
> A special thank you to all our contributors for making this possible. We
> had 780 commits from 48 unique contributors over the past few months. It's
> quite an achievement. We look forward to your continued support in our
> v21.2 release!
>
>
>
> Kind regards,
>
> Bobby
>
> --
>
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
>
>
> web: https://www.bobbybruce.net
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[gem5-users] Re: ARM KVM

2021-07-12 Thread Jason Lowe-Power via gem5-users
To use hardware-accelerated virtualization (i.e., KVM) your host and guest
must have the same ISA (and the host must have virtualization extension).

Cheers,
Jason

On Mon, Jul 12, 2021 at 12:17 PM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 community,
>
> I have installed the latest gem5 on an x86 machine. Is it possible to
> run ARM FS with kvm on X86 machine or the host machine must be
> ARM-based?
>
> I try to execute the following configuration (from this thread
> https://www.mail-archive.com/gem5-users@gem5.org/msg19472.html):
>
> $GEM5/build/ARM/gem5.opt $GEM5/configs/example/arm/fs_bigLITTLE.py
> --kernel=vmlinux.arm64 --machine-type VExpress_GEM5 --disk
> ubuntu-18.04-arm64-docker.img --cpu-type kvm --big-cpus 4
>
> and I get the following error (which means that there is not the kvm
> option):
>
> fs_bigLITTLE.py: error: argument --cpu-type: invalid choice: 'kvm'
> (choose from 'atomic', 'timing', 'exynos')
>
> May you help me, please?
>
> Best regards,
> Nikos
>
>
>
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[gem5-users] Re: Custom SimObject Causes Host Machine to Freeze

2021-07-06 Thread Jason Lowe-Power via gem5-users
Hi Sam,

My suggestion would be to use gdb. You can run gem5 in gdb and then use
ctrl-c to stop the execution and see where the program is getting stuck.
Also, enabling debug flags (or just good ole printf debugging) can also be
useful in these cases.

Another option with gdb would be to put breakpoints on each of the
functions in your object (e.g., the constructor) and then step through to
see what's happening.

A final thought... does your object enqueue any events? If so, are the
enqueued *in the future*? If you enqueue an event at the current tick
(curTick()) and then that event enqueues an event at the current tick you
can get stuck in an infinite loop. (The Event debug flag could be useful
here, too.)

Cheers,
Jason

On Tue, Jul 6, 2021 at 8:56 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I'm writing because I'm working with a custom SimObject that I wrote that
> seems to crash my host machine. I know it's this particular SimObject
> because the script works as expected when run without the object, but it
> makes debugging an excruciatingly difficult process.
>
> Is this an issue that anyone has seen before? And if so, does anyone have
> any hints as to what might be causing the host to crash?
>
> Thank you for your help!
>
> Best,
> Sam
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[gem5-users] Re: question about RSCV-V implementation on Gem5

2021-07-05 Thread Jason Lowe-Power via gem5-users
See https://gem5.atlassian.net/browse/GEM5-618

On Sat, Jul 3, 2021 at 5:23 PM lovline via gem5-users 
wrote:

> Hi,
>We are working on an important project, and we want to use RSCV-V1.0
> vector instructions on Gem5.
>But we cann't find any features or codes about RSCV-V on Gem5.
>We searched the mail-list also did not find the plan for RSCV-V1.0.
>So we send this mail.
>Please help us, thank you very much.
>
>
> Regards,
> Will
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[gem5-users] Re: does gem5 have a C++ API?

2021-07-02 Thread Jason Lowe-Power via gem5-users
Hello,

Unfortunately, I don't think gem5 is the right tool for this job. When you
run that command, gem5's embedded python interpreter is executing `se.py`.
There's not really a way to easily get around this. You could try to
compile gem5 without python (--without-python, IIRC), but then configuring
the system you're running is difficult, if not impossible, depending on the
system you want to simulate.

Cheers,
Jason

On Thu, Jul 1, 2021 at 6:06 PM Konstantin Serebryany <
konstantin.s.serebry...@gmail.com> wrote:

> Hi Jason,
>
> Thanks for the reply!
> I was hoping for something light-weight, similar to Unicorn, but based on
> gem5 instead of QEMU...
>
> I tried running
>   build/X86/gem5.opt configs/example/se.py -c
> ./tests/test-progs/hello/bin/x86/linux/hello
> and it takes 0.3 second -- too slow.
>
> The profile shows:
>   14.55%  gem5.opt  libpython3.9.so.1.0[.] _PyEval_EvalFrameDefault
>
>
>
>2.31%  gem5.opt  libpython3.9.so.1.0[.] _PyType_Lookup
>
>
>
>2.01%  gem5.opt  libpython3.9.so.1.0[.]
> _PyObject_GenericGetAttrWithDict
>
>
>1.09%  gem5.opt  libpython3.9.so.1.0[.] _Py_CheckFunctionResult
>
>
>
>1.06%  gem5.opt  libpython3.9.so.1.0[.] 0x002000b0
>
>
>
> ...
> I.e. all the time for simulating a tiny test is spent in python.
>
> I'd like to be able to simulate tiny programs, like "hello" from the
> examples,
> but hopefully at least 100x faster than this.
>
> What's the best supported mechanism for running many tiny simulations
> w/o having to pay for the large python overhead?
> Any examples?
>
> --kcc
>
>
>
>
>
>
> On Thu, Jul 1, 2021 at 5:00 PM Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> It's somewhat possible. You can compile gem5 as a library (e.g., scons
>> build//libgem5-opt.so). However, gem5 *is a python
>> interpreter* and is configured via python scripts. Getting that to work
>> with an external program is "exciting". It's possible to get python
>> working, and there are other workarounds like using the CXXConfig
>> interface, but it's not straightforward or easy to understand.
>>
>> Unless you're trying to integrate gem5 into another simulator, it's
>> unlikely that invoking gem5 from another program is the best option. Even
>> in this case, I would advise going the other way and using gem5 as the
>> driver simulator. That said, there are many simulators that integrate with
>> gem5. You can easily hook in things like DRAMSim, at one point I integrated
>> it with GPGPU-Sim (this is now incredibly out of date), and there is an
>> SST-gem5 bridge that we are actively working on. Finally, there are many
>> efforts to integrate gem5 with SystemC including implementing the entire
>> SystemC spec in gem5.
>>
>> Hopefully this helps. I'd be happy to provide more specific help with
>> some more information :).
>>
>> Cheers,
>> Jason
>>
>> On Thu, Jul 1, 2021 at 4:49 PM Konstantin Serebryany via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,
>>>
>>> [gem5 newbie here... ]
>>>
>>> Does gem5 have a C++ API?
>>>
>>> I am interested in using gem5 as a library, i.e. invoking
>>> the system call emulation mode from within my process,
>>> without fork/exec or python.
>>> Is that at all possible?
>>> Any pointers?
>>>
>>> thanks!
>>>
>>> --kcc
>>>
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>>
>>
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[gem5-users] Re: does gem5 have a C++ API?

2021-07-01 Thread Jason Lowe-Power via gem5-users
Hello,

It's somewhat possible. You can compile gem5 as a library (e.g., scons
build//libgem5-opt.so). However, gem5 *is a python
interpreter* and is configured via python scripts. Getting that to work
with an external program is "exciting". It's possible to get python
working, and there are other workarounds like using the CXXConfig
interface, but it's not straightforward or easy to understand.

Unless you're trying to integrate gem5 into another simulator, it's
unlikely that invoking gem5 from another program is the best option. Even
in this case, I would advise going the other way and using gem5 as the
driver simulator. That said, there are many simulators that integrate with
gem5. You can easily hook in things like DRAMSim, at one point I integrated
it with GPGPU-Sim (this is now incredibly out of date), and there is an
SST-gem5 bridge that we are actively working on. Finally, there are many
efforts to integrate gem5 with SystemC including implementing the entire
SystemC spec in gem5.

Hopefully this helps. I'd be happy to provide more specific help with some
more information :).

Cheers,
Jason

On Thu, Jul 1, 2021 at 4:49 PM Konstantin Serebryany via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> [gem5 newbie here... ]
>
> Does gem5 have a C++ API?
>
> I am interested in using gem5 as a library, i.e. invoking
> the system call emulation mode from within my process,
> without fork/exec or python.
> Is that at all possible?
> Any pointers?
>
> thanks!
>
> --kcc
>
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[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian,

The AMD GPU model has never been tested with Arm. I doubt the ROCm stack
will compile/work with any ISA other than x86, unfortunately.

For multi-GPU support see
http://www.gem5.org/2020/05/30/enabling-multi-gpu.html

Of course, multiple CPUs will work with no problem with or without GPU(s).

Cheers,
Jason

On Wed, Jun 30, 2021 at 8:05 AM adrian via gem5-users 
wrote:

> Hi Jason,
>
> Thanks a lot for this useful information.
> Is it possible to have several CPUs + several GPUs running in parallel?
> I'm using Arm as the CPU's ISA. I don't know how this GPU ISA deals with
> other ISAs.
>
> Sincerely,
> Adrián
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[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian,

gem5 has support for AMD's GCN3 (compute) GPU in SE mode, and we're working
on merging both Vega support (AMD's newer GPU ISA) and full system support.
The status of these new features can be followed on Jira.

Here's documentation on the current GPU support:
http://www.gem5.org/documentation/general_docs/gpu_models/GCN3
http://www.gem5.org/2020/05/27/modern-gpu-applications.html

Also, there are a number of resources to help you get started. For instance:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/hip-samples/
https://resources.gem5.org/resources/dnn-mark (available soon, as in about
15 minutes after I send this email)

Cheers,
Jason

On Wed, Jun 30, 2021 at 7:05 AM adrian via gem5-users 
wrote:

> Hi,
>
> I am interested in simulating a GPU in gem5. Just by googling I discovered
> a repo from 2017 but I've also seen gem5 v21 has some files regarding to
> the GPU.
> Could you please confirm gem5 v21 supports a GPU model? There is not much
> info about it on internet. How can this GPU model be used?
>
> Many thanks,
> Sincerely,
> Adrián
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[gem5-users] Re: Fatal error while running multithreaded program in SE mode

2021-06-25 Thread Jason Lowe-Power via gem5-users
What version of gem5 are you using? I believe gem5-20.0+ has the getdents
syscall implemented. I'm sure that 21.0 has the syscall implemented.
Whether you're using Ruby or classic caches it shouldn't make
any difference on whether the syscalls are implemented.

Cheers,
Jason

On Fri, Jun 25, 2021 at 3:32 AM hissa alshamsi via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
>
>
>
> I am trying to run a multithreaded program in SE mode, after installing
> m5thread and following the steps in
> https://github.com/WeijingShi/playground/blob/master/Run-openmp-code-in-gem5.md
>
>
>
> But I keep getting that syscall getdents unimplemented.
>
>
>
> This is the line I have used:
>
> build/X86/gem5.opt configs/example/se.py --cpu-type=TimingSimpleCPU
> –cpu-cycle=2GH-n 8 --cmd=m5threads/tests/test_omp -o '8 8'
>
>
>
>
>
>  REAL SIMULATION 
>
> info: Entering event queue @ 0.  Starting simulation...
>
> warn: Attempting to open special file: /sys/devices/system/cpu. Ignoring.
> Simulation may take un-expected code path or be non-deterministic until
> proper handling is implemented.
>
> fatal: syscall getdents (#78) unimplemented.
>
> Memory Usage: 829528 Kbytes
>
>
>
> Any clue on how to run a multithreaded program in SE mode without using
> ruby?
>
>
>
> Thank you in advance,
>
> Hessa.
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[gem5-users] Re: gem5 RISCV, issue on boot when mounting filesystem

2021-06-25 Thread Jason Lowe-Power via gem5-users
Hi everyone,

These details on gem5-resources have also been tested multiple times. We
have also gotten unmodified OpenSBI working with gem5 as well. Ayaz can
provide more details if you need.

https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/riscv-fs/

Cheers,
Jason

On Fri, Jun 25, 2021 at 8:22 AM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:

> Dear David,
>
> I have used the bbl, Linux Kernel, and riscv_disk from the following
> GitHub: https://github.com/ppeetteerrs/gem5-RISC-V-FS-Linux/ .You can
> use either the files from prebuild directory or you can create your
> own according to instructions of this Github. Specifically, I have
> used the following configurations which are working properly (5 of 6):
>
>  RISCV 1 core 
>
> AtomicSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=AtomicSimpleCPU
> --disk-image=$OUT/riscv_disk -n 1
>
>
> TimingSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=TimingSimpleCPU
> --disk-image=$OUT/riscv_disk -n 1
>
> DerivO3CPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=DerivO3CPU
> --disk-image=$OUT/riscv_disk -n 1
>
>
>  RISCV 2 cores 
>
> AtomicSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=AtomicSimpleCPU
> --disk-image=$OUT/riscv_disk -n 2
>
> TimingSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=TimingSimpleCPU
> --disk-image=$OUT/riscv_disk -n 2
>
> DerivO3CPU (NOT Working): void BaseDynInst< 
>  >::initVars() [with Impl = O3CPUImpl]: Assertion `cpu->instcount <=
> 1500' failed.
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=DerivO3CPU
> --disk-image=$OUT/riscv_disk -n 2
>
>
> To be noticed that when I use --mem-size more than 512MB, gem5 is not
> booted.
>
>
> Finally, when I use the last configuration I get the above error
> (please let me know if you/anyone can resolve it :))
>
> Best regards,
> Nikolaos Tampouratzis
>
>
> Quoting Truan David via gem5-users :
>
> > Hello,
> > We are a team working on gem5 RISCV. We are trying to use gem5
> > full-system but we are encountering some issues when mounting the
> > rootfs/initramfs.
> >
> > This is our setup:
> > - gem5 on branch develop from
> > https://gem5.googlesource.com/public/gem5 (c493d2c4ad)
> > - BBL on branche master from https://github.com/riscv/riscv-pk.git
> (e8e6b3aa)
> > - Linux 5.10, checkout on v5.10 tag (2c85ebc57)
> >
> > This is what we tried so far:
> >
> > -Compiling BBL with and without specifying the DTS: No changes
> > -Compiling BBL with Linux vmlinux OR Image as payload: No changes
> > -Compiling Linux with an minimalistic initramfs which only prints a
> > "Hello World" from the init script: No changes
> > -Using fs_linux.py OR run_riscv.py as the entry point: No changes
> >
> > Here are the boot logs from different experiments, with only the
> > last lines of the boot log to keep this mail short:
> >
> > =
> > This is the boot log when specifying a disk-image param, using
> fs_linux.py:
> >
> > Command:
> > $GEM5_FAST_BIN -v \
> > -d $GEM5_OUTPUT \
> > $GEM5_HOME/configs/example/riscv/fs_linux.py \
> > --cpu-type=AtomicSimpleCPU \
> > --cpu-clock=1GHz \
> > -n 1 \
> > --disk-image=$DISK \
> > --kernel= \
> > --mem-type=DDR4_2400_4x16 \
> > --mem-size=4GB \
> > --command-line="root=/dev/vda ro console=ttyS0"
> >
> >
> >  m5 terminal: Terminal 0 
> > ...
> > [1.123014] [drm] radeon kernel modesetting enabled.
> > [1.146199] loop: module loaded
> > [1.147219] virtio_blk virtio0: [vda] 6821 512-byte logical
> > blocks (3.49 MB/3.33 MiB)
> > [1.147423] vda: detected capacity change from 0 to 3492352
> >
> > =
> > This is the boot log when NOT specifying a disk-image param, using
> > fs_linux.py:
> >
> > Command:
> > $GEM5_FAST_BIN -v \
> > -d $GEM5_OUTPUT \
> > $GEM5_HOME/configs/example/riscv/fs_linux.py \
> > --cpu-type=AtomicSimpleCPU \
> > --cpu-clock=1GHz \
> > -n 1 \
> > --kernel= \
> > --mem-type=DDR4_2400_4x16 \
> > --mem-size=4GB \
> > --command-line="root=/dev/vda ro console=ttyS0"
> >
> >  m5 terminal: Terminal 0 
> > ...
> > [1.121246] [drm] radeon kernel modesetting enabled.
> > [1.144593] loop: 

[gem5-users] Re: Understanding write timing in MemCtrl

2021-06-22 Thread Jason Lowe-Power via gem5-users
Hi Vincent,

It depends on when/how you're ending the simulation. If you end the
simulation at some particular tick, then you'll see writes left in the
write queue. Just like a real machine, writes don't happen instantaneously,
and at some point in time, there are writes sitting in the write buffer
(and dirty data in the cache, too). In gem5, like a real system, if you
wanted to ensure everything is flushed to persistent storage, you could
call a flush system call. Also like a real system, there is no instruction
to flush the memory controller write queues. The data there is
architecturally visible, so it doesn't matter if it's in the write queue or
in memory.

If for some reason you really need all of the data in gem5's backing memory
(e.g., to take a checkpoint), you can call the drain() function which will
dump everything.

I believe you're really asking about timing accuracy, though. If that's the
case, I would give you two comments: (1) I would expect that your program
runs long enough that 32 cache lines that haven't been written back to
memory will make no difference in the overall execution time. And (2) if
you really need to be modeling that this detailed of a level, you should
probably be using full system mode so you can correctly model syscalls, etc.

Hopefully this answers your question!

Cheers,
Jason

On Tue, Jun 22, 2021 at 8:06 AM Vincent R. via gem5-users <
gem5-users@gem5.org> wrote:

> Hi again,
>
> just wanted to give this a second try. No urgent matter here, just some
> lack of understanding and curiosity on my side.
>
> Thank you,
> Vincent
>
>
> Am 04.06.2021 um 11:34 schrieb Vincent R.:
> > Hi everyone,
> >
> > I am currently doing some experiments with packet timings in the
> > Memory Controller( gem5 version 20.1.0.2., SE mode). As I understood
> > it, writes accesses are serviced instantly by the controller and their
> > actual timing is only calculated later when the corresponding
> > nextReqEvent is processed and the packet is removed from the write queue.
> > This works fine, however, with default parameters set, there are still
> > a lot of write packets left in the queue, when the simulation exits.
> > So, in my understanding, these are never correctly timed.
> >
> > As I was experimenting I set the write threshold parameters of MemCtrl
> > in a way to force the controller to process all writes. Naturally the
> > run time increases by a large amount of ticks.
> >
> > My question: How does gem5 perform a correct timing simulation while
> > leaving untimed writes in the queue at the end of simulation? Or
> > doesn't it? Have I misunderstood something?
> >
> > Test system is a simple example configuration without caches.
> >
> >
> > Thank you for your help.
> > Vincent
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