[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

2021-10-12 Thread Jason Lowe-Power via gem5-users
I would suggest using DPRINTF instead of cout. It's possible that some
print statements aren't being flushed.

Jason

On Mon, Oct 11, 2021 at 7:16 AM Sampad Mohapatra  wrote:

> Hi Jason,
>
> I have added a std::cout statement to the resetstats()'s body and I am
> calling m5_reset_stats from my GPU benchmarks.
> The GPU kernels are launched right after reset is called. I pipe the
> output of simulations to a file. But, strangely enough
> some outputs show the std::cout statements while others don't. What could
> be the reason ?
>
> Thanks,
> Sampad
>
> On Mon, Oct 4, 2021 at 12:08 PM Jason Lowe-Power 
> wrote:
>
>> Hi Sampad,
>>
>> Here is where m5_reset_stats is implemented in the simulator:
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303
>>
>> There are a large number of steps between when the guest code calls
>> m5_reset_stats and when the above function executes, but this should help
>> you start hacking :).
>>
>> Cheers,
>> Jason
>>
>> On Sat, Oct 2, 2021 at 4:05 AM Sampad Mohapatra via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi All,
>>>
>>> I need to set a bool variable in src/cpu/simple/base.(hh|cc) to be true
>>> when m5_reset_stats() is *explicitly *called from some binary executing
>>> on gem5. Using this bool and instruction count, I want to exit the
>>> simulation.
>>>
>>> How can I modify the body (hack) of m5_reset_stats() to call other
>>> functions ? Where is its body defined ?
>>> If not possible, then is there any alternative way to set the bool
>>> variable when m5_reset_stats() is *explicitly* called ?
>>>
>>> Thank You,
>>> Sampad Mohapatra
>>>
>>>
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>>
>>
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[gem5-users] Re: Seg. Fault while "Creating a simple configuration script"

2021-10-08 Thread Jason Lowe-Power via gem5-users
Hello,

Does the file configs/learning_gem5/part1/simple.py work for you? If so,
then there is probably a small mistake in your configuration script. If
this is the case, can you send your script (maybe off list)? I would like
to understand the problem and improve the error message.

Cheers,
Jason

On Fri, Oct 8, 2021 at 12:35 AM saheed - via gem5-users 
wrote:

> Hello,
>
> I am following the Getting started instructions, I am stuck at the
> beginning!
> "Creating a simple configuration script".
>
> I am using the current stable version of gem5 on a Debian (buster) system.
>
> 1. `build/X86/mem/mem_interface.cc:793: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)`
>
>  I managed to fix this by increasing `system.mem_ranges` to 8GB.
> Buried somewhere on the internet is a comment about something defaulting to
> 8GB.
>
> 2. `warn: No dot file generated. Please install pydot to generate the dot
> file and pdf.`
>
>   I have installed this with `sudo apt install python-pydot
> python-pydot-ng graphviz` . Could this be because my system is running in
> server mode (no GUI)?
>
> 3. *The SEG. FAULT:*
> Here is the whole load down, please let me know what I am doing wrong
>
> ~/DEV/comp-arch/gem5$ build/X86/gem5.opt configs/tutorial/simple.py
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.1.0.2
> gem5 compiled Oct  8 2021 08:16:42
> gem5 started Oct  8 2021 09:27:49
> gem5 executing on saheed-deb, pid 22197
> command line: build/X86/gem5.opt configs/tutorial/simple.py
>
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
> Beginning simulation!
> build/X86/sim/simulate.cc:107: info: Entering event queue @ 0.  Starting
> simulation...
> gem5 has encountered a segmentation fault!
>
> --- BEGIN LIBC BACKTRACE ---
> build/X86/gem5.opt(+0x9275b9)[0x55a3a34815b9]
> build/X86/gem5.opt(+0x9417ff)[0x55a3a349b7ff]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12730)[0x7f63c4fbf730]
> build/X86/gem5.opt(+0x986654)[0x55a3a34e0654]
> build/X86/gem5.opt(+0x4b9847)[0x55a3a3013847]
> build/X86/gem5.opt(+0x4b21a5)[0x55a3a300c1a5]
> build/X86/gem5.opt(+0x4b2e18)[0x55a3a300ce18]
> build/X86/gem5.opt(+0x933e75)[0x55a3a348de75]
> build/X86/gem5.opt(+0x95aad1)[0x55a3a34b4ad1]
> build/X86/gem5.opt(+0x95b2a2)[0x55a3a34b52a2]
> build/X86/gem5.opt(+0xe7d3ce)[0x55a3a39d73ce]
> build/X86/gem5.opt(+0x39276d)[0x55a3a2eec76d]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyCFunction_Call+0xfb)[0x7f63c5243b5b]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x78e0)[0x7f63c5044700]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyFunction_FastCallKeywords+0x93)[0x7f63c5243123]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x7b95)[0x7f63c50449b5]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f63c516c46e]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCode+0x1b)[0x7f63c516d23b]
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(+0x1a2bdd)[0x7f63c5170bdd]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyMethodDef_RawFastCallKeywords+0x2a5)[0x7f63c5242c75]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyCFunction_FastCallKeywords+0x25)[0x7f63c5243a05]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x8bde)[0x7f63c50459fe]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyFunction_FastCallKeywords+0x93)[0x7f63c5243123]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x7b95)[0x7f63c50449b5]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f63c516c46e]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCode+0x1b)[0x7f63c516d23b]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyRun_StringFlags+0x8b)[0x7f63c513afeb]
> build/X86/gem5.opt(+0x93fa1f)[0x55a3a3499a1f]
> --- END LIBC BACKTRACE ---
> Segmentation fault
>
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[gem5-users] Re: Porting a configuration file from gem5 v20 to gem5 v21

2021-10-06 Thread Jason Lowe-Power via gem5-users
Hi Ali,

Is your guest code 32-bit Arm? If so, I think this could be the problem in
SE mode: https://gem5.atlassian.net/browse/GEM5-1074

Cheers,
Jason

On Tue, Oct 5, 2021 at 7:45 AM Ali Ghandour via gem5-users <
gem5-users@gem5.org> wrote:

> In FS mode, full errror stack below:
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/ARM/python/m5/main.py", line 455, in main
>   File "./RPIv4.py", line 535, in 
> main()
>   File "./RPIv4.py", line 512, in main
> root.system = systemCreate(args)
>   File "./RPIv4.py", line 297, in systemCreate
> system = RPISystemCreate(ArmSystem, args, mode)
>   File "./RPIv4.py", line 182, in RPISystemCreate
> return RPISystem(args, mode)
>   File "./RPIv4.py", line 127, in __init__
> self.configMem(args)
>   File "./RPIv4.py", line 158, in configMem
> self.cpu_cluster.connectDirect(self.membus)
>   File
> "/home/ali/Desktop/spirals/reproduce-spectre-gem5/gem5/./ARMv8A_Cortex_A72.py",
> line 325, in connectDirect
> cpu.dtb.walker.port = bus.slave
>   File "build/ARM/python/m5/SimObject.py", line 1416, in __getattr__
> AttributeError: object 'ARM_A72_TLB_L1D' has no attribute 'walker'
>   (C++ object is not yet constructed, so wrapped C++ methods are
> unavailable.)
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[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

2021-10-04 Thread Jason Lowe-Power via gem5-users
Hi Sampad,

Here is where m5_reset_stats is implemented in the simulator:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303

There are a large number of steps between when the guest code calls
m5_reset_stats and when the above function executes, but this should help
you start hacking :).

Cheers,
Jason

On Sat, Oct 2, 2021 at 4:05 AM Sampad Mohapatra via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> I need to set a bool variable in src/cpu/simple/base.(hh|cc) to be true
> when m5_reset_stats() is *explicitly *called from some binary executing
> on gem5. Using this bool and instruction count, I want to exit the
> simulation.
>
> How can I modify the body (hack) of m5_reset_stats() to call other
> functions ? Where is its body defined ?
> If not possible, then is there any alternative way to set the bool
> variable when m5_reset_stats() is *explicitly* called ?
>
> Thank You,
> Sampad Mohapatra
>
>
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[gem5-users] Re: Get Size of Stack and Heap

2021-09-30 Thread Jason Lowe-Power via gem5-users
Hi Ange,

If you're using SE mode, you may be able to augment the allocation code to
track the heap size. E.g.,
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/mem_state.cc#108

In fact, the MemState object tracks both the stack and the heap, so you can
get a lot of information from that. Again, this assumes you're using SE
mode.

If you're using FS mode, it will be a bit more complicated. You're on the
right track with the readArchInReg. I'm not sure exactly how Arm tracks the
heap, but I would dig into the remote GDB implementation to see if there
are any hints in that code.

Cheers,
Jason

On Thu, Sep 23, 2021 at 9:46 AM Ange via gem5-users 
wrote:

> Hi all,
>
> I am trying to keep track of the size of the stack and heap while
> executing a binary, and at the moment, I can get the address of the stack
> pointer using this line of code
> cpu->readArchIntReg(ArmISA::INTREG_SP ,tid).
> I am also trying to read the frame pointer (FP), but I am having trouble
> getting the address for it
> because it always prints zero as its address, and I am using Register 11
> for the FP (cpu->readArchIntReg(ArmISA::INTREG_R11) ).
> Am I doing something wrong, or is there a better way to get the stack
> size?  and also the heap size with its addresses?
>
> I saw that someone asked a similar question a while back on this forum,
> but it was not fully answered.
> Here is the link
> https://www.mail-archive.com/gem5-users@gem5.org/msg04154.html
>
> I need help!
>
> Ange
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[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
Yeah. I would suggest working on a native linux machine if you're going to
use KVM. If you're not using KVM, then WSL *should* (no promises ;)) work
OK.

Cheers,
Jason

On Thu, Sep 23, 2021 at 3:21 PM Reiko Matsuda-dunn <
reiko.matsudad...@colorado.edu> wrote:

> Thanks for the resources! Seems like quite a can of worms.It's almost
> looking like it could be easier to partition a computer for Linux and start
> over. Would you recommend that as an alternative?
>
> All th
>
> On Thu, Sep 23, 2021 at 1:36 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi Reiko,
>>
>> The KVM CPU requires that the host platform supports KVM. Given that
>> you're using WSL, this means that you need to have nested virtualization
>> enabled and implemented on your WSL kernel.
>> https://www.reddit.com/r/bashonubuntuonwindows/comments/ldbyxa/what_is_the_current_state_of_kvm_acceleration_on/
>> has more information.
>>
>> We can try to help you with this, but currently we only support KVM on
>> native Linux hosts.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Sep 23, 2021 at 11:36 AM Reiko Matsuda-dunn via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hello,
>>>
>>> I'm trying to troubleshoot this error (output below).  I've looked at
>>> prior posts in this mailing list and was able to change perf_event_paranoid
>>> to -1 ( I confirmed this with $cat /proc/sys/kernel/perf_event_paranoid,
>>> which returns -1, although it resets to 2 every time I reboot). It looks
>>> like there's some mention of a patch, but I haven't been able to find that
>>> patch. If anyone could point me to that, or offer other suggestions I would
>>> be grateful!
>>>
>>> I'm using gem5 21, WSL2, and have otherwise follower the tutorial here:
>>> https://www.gem5.org/documentation/gem5art/tutorials/spec-tutorial
>>> <https://secure-web.cisco.com/17IBO0xQxkZZIebcGCBpl1G0BsdiJYaESwCqShOyCJRixJFvPEMpbaePLfLril03_Qv4GGBoSf1-s_RSxDFuTNEd3nZ6jb0A1cTSgSVFF0TlW1yWTMajw2VxDcgoQK9MBNdDMxXseHmenbOhFoHzv2_nSqldKvC5u8wj1QXxh6AWAgT-lqcyDlX3wNkRQ-RubhrlVql0h1nLr5X3xLcaS9VTm2VvIJRRkiCZ9AUQeNGn0Tw2BWM1jWjW9qSghZtSB-ir8AP83Di1pPW25Q2ALWnuR-YoVfQ9JL4eL6Aql49G8VUkDU4LtTjLHprwIYfe7xfz-J2mBNwAs6Cy_qgF8Z7M1c6GbEc_4GBF_QUvdVYZhz4L46EEpidbJb2txcdtl4NghPNs9ua1gBj5wynZ2j1GynRoxrrc_Y_sJnfR_xMQxGI9EcqCfe9zm2-St2Zq3clFno40v_7K-s8JTR5a8GA/https%3A%2F%2Fwww.gem5.org%2Fdocumentation%2Fgem5art%2Ftutorials%2Fspec-tutorial>
>>>
>>> My launch_spec2017_experiment.py has been modified slightly for the
>>> paths and gem5 version.
>>>
>>> Thanks for all your help,
>>> Reiko
>>>
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (128 Mbytes)
>>> build/X86/sim/kernel_workload.cc:46: info: kernel located at:
>>> vmlinux-4.19.83
>>> build/X86/dev/serial/terminal.cc:170: warn:
>>> Sockets disabled, not accepting terminal connections
>>> build/X86/base/remote_gdb.cc:377: warn:
>>> Sockets disabled, not accepting gdb connections
>>> build/X86/mem/coherent_xbar.cc:140: warn:
>>> CoherentXBar system.cpu.mmucache.mmubus has no snooping ports attached!
>>> build/X86/dev/intel_8254_timer.cc:125: warn:
>&g

[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Reiko,

The KVM CPU requires that the host platform supports KVM. Given that you're
using WSL, this means that you need to have nested virtualization enabled
and implemented on your WSL kernel.
https://www.reddit.com/r/bashonubuntuonwindows/comments/ldbyxa/what_is_the_current_state_of_kvm_acceleration_on/
has more information.

We can try to help you with this, but currently we only support KVM on
native Linux hosts.

Cheers,
Jason

On Thu, Sep 23, 2021 at 11:36 AM Reiko Matsuda-dunn via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I'm trying to troubleshoot this error (output below).  I've looked at
> prior posts in this mailing list and was able to change perf_event_paranoid
> to -1 ( I confirmed this with $cat /proc/sys/kernel/perf_event_paranoid,
> which returns -1, although it resets to 2 every time I reboot). It looks
> like there's some mention of a patch, but I haven't been able to find that
> patch. If anyone could point me to that, or offer other suggestions I would
> be grateful!
>
> I'm using gem5 21, WSL2, and have otherwise follower the tutorial here:
> https://www.gem5.org/documentation/gem5art/tutorials/spec-tutorial
> My launch_spec2017_experiment.py has been modified slightly for the paths
> and gem5 version.
>
> Thanks for all your help,
> Reiko
>
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (128 Mbytes)
> build/X86/sim/kernel_workload.cc:46: info: kernel located at:
> vmlinux-4.19.83
> build/X86/dev/serial/terminal.cc:170: warn:
> Sockets disabled, not accepting terminal connections
> build/X86/base/remote_gdb.cc:377: warn:
> Sockets disabled, not accepting gdb connections
> build/X86/mem/coherent_xbar.cc:140: warn:
> CoherentXBar system.cpu.mmucache.mmubus has no snooping ports attached!
> build/X86/dev/intel_8254_timer.cc:125: warn:
> Reading current count from inactive timer.
> build/X86/cpu/kvm/base.cc:152: info: KVM:
> Coalesced MMIO disabled by config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/cpu/kvm/base.cc:152: info: KVM:
> Coalesced MMIO disabled by config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/sim/simulate.cc:107: info:
> Entering event queue @ 0.  Starting simulation...
> build/X86/cpu/kvm/perfevent.cc:183: panic:
> PerfKvmCounter::attach failed (2)
> Memory Usage: 8738772 KBytes
> build/X86/cpu/kvm/perfevent.cc:183: panic:
> PerfKvmCounter::attach failed (2)
> Memory Usage: 8738772 KBytes
> Program aborted at tick 0
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[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Xihui,

The error is "died with "

I would guess you're out of memory or trying to compile too many files at
once. But, it could be many different problems. If it's an issue with
dependencies or your host, you can always use our docker images:
https://www.gem5.org/documentation/general_docs/building#:~:text=dev%20pkg-config-,Docker,-For%20users%20struggling

Cheers,
Jason

On Thu, Sep 23, 2021 at 1:01 AM Xihui Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
>   Thanks for your help.
>   But there are lots of errors in the first time to build gem5.
>
> scons: *** [build/X86/mem/ruby/protocol/DMA_Controller.py.cc]
> CalledProcessError : Command '['/home/xihui/下载/gem5/build/X86/marshal',
> 'build/X86/mem/ruby/protocol/DMA_Controller.py']' died with
> .
> Traceback (most recent call last):
>   File "/usr/lib/scons/SCons/Action.py", line 1209, in execute
> result = self.execfunction(target=target, source=rsources, env=env)
>   File "/home/xihui/下载/gem5/build/X86/SConscript", line 1293, in
> embedPyFile
> marshalled = subprocess.check_output(
>   File "/usr/lib/python3.8/subprocess.py", line 415, in check_output
> return run(*popenargs, stdout=PIPE, timeout=timeout, check=True,
>   File "/usr/lib/python3.8/subprocess.py", line 516, in run
> raise CalledProcessError(retcode, process.args,
> subprocess.CalledProcessError: Command
> '['/home/xihui/下载/gem5/build/X86/marshal',
> 'build/X86/mem/ruby/protocol/DMA_Controller.py']' died with
> .
> scons: building terminated because of errors.
>
> Do you have any opinion or suggestion?
>
>
> Regards,
> Xihui
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[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-20 Thread Jason Lowe-Power via gem5-users
Hi Xihui,

That's just a warning and you can safely ignore it. The most recent hotfix
release should remove this warning as well.

Cheers,
Jason

On Sun, Sep 19, 2021 at 10:02 PM Xihui Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone:
>
> I am a beginner with GEM5.
> There was a problem when I ran the project for the first time.
>
> Warning: Deprecated names are not supported by the compiler.
>
> I found no solution in the mailing list and website.
> Could you please give me any help to fix it?
>
> Thanks.
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[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Sam,

I would *guess* it's the draining code getting stuck in an infinite loop.
The draining code calls "drain" on all SimObjects in the system, and they
do their thing. Then, the drain code asks all SimObjects if they're done
draining. If not, it starts over and calls drain on all objects again. If
some object isn't draining properly or if there is some circular
dependence, there could be a "live lock" in this code. Just a guess, though.

Cheers,
Jason

On Wed, Sep 8, 2021 at 10:00 AM Thomas, Samuel 
wrote:

> Hi Jason,
>
> Thanks for your help. I think I've honed in on the source of the problem
> -- namely, number of cpus. Is there a reason why having multiple CPUs in a
> particular configuration would limit the simulator's ability to write a
> checkpoint?
>
> Again, thank you for your help!
>
> Best,
> Sam
>
> On Wed, Sep 8, 2021 at 11:12 AM Jason Lowe-Power 
> wrote:
>
>> Hi Sam,
>>
>> Sorry for the frustration. Writing better documentation is always #2 on
>> the priority list :(.
>>
>> I always tell people not to trust any of the "options" to fs.py and
>> se.py. Those scripts have gotten so far beyond "out of hand" at this point
>> that they are almost useless. They are trying to be everything to everyone,
>> and they end up just being a mess of spaghetti code and confusion.
>>
>> To take a checkpoint, you can add the following code to a python
>> runscript:
>>
>> m5.simulate(1)
>> m5.checkpoint()
>> m5.simulate(2)
>> m5.checkpoint()
>>
>> I tested the above code by adding it to the
>> configs/learning_gem5/part1/two_level.py file.
>>
>> *Maybe* this is what --take-checkpoints is doing. It's certainly what it
>> was *supposed* to do, but again, since this code has gotten so out of hand,
>> who knows if it's actually doing what it advertises.
>>
>> If you want to use the m5ops to checkpoint, the code would look
>> something like the following (this isn't tested and it's off the top of my
>> head).
>>
>> while 1:
>>   exit_event = m5.simulate()
>>   if exit_event.getCause() == 'checkpoint'):
>> m5.checkpoint(m5.outdir + '/' + str(num))
>>   else:
>> break
>>
>> To restore from a checkpoint, pass the checkpoint directory as the only
>> parameter to m5.instantiate(ckpt_dir=).
>>
>> Hope this helps! If you're still experiencing a hang in this case, it's
>> probably a bug in the drain() code somewhere. You can try to use one of the
>> drain debug flags (I don't know exactly what these are... check gem5
>> --debug-help for a list of debug flags). Making the python runscript do
>> exactly what you expect will also help with debugging. When you control the
>> script, adding prints is easy, too!
>>
>> Finally, the file src/python/m5/simulate.py may be helpful to figure out
>> what's going on when instantiating, simulating, checkpointing, etc.
>>
>> Cheers,
>> Jason
>>
>> On Wed, Sep 8, 2021 at 6:14 AM Thomas, Samuel via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi all,
>>>
>>> Just to follow up, because I can see that there have been some issues
>>> with not including all of the requisite issues in other threads, here is
>>> the full output from what I described above.
>>>
>>> gem5 Simulator System.  http://gem5.org
>>> gem5 is copyrighted software; use the --copyright option for details.
>>>
>>> gem5 version 21.1.0.0
>>> gem5 compiled Sep  7 2021 19:28:16
>>> gem5 started Sep  8 2021 09:09:11
>>> gem5 executing on sam-Precision-Tower-5810, pid 445665
>>> command line: build/X86/gem5.opt -d $CURR_DIR/debug
>>> $CURR_DIR/configs/example/fs.py --caches --l2cache --mem-type DDR3_1600_8x8
>>> --mem-size 2GB --meta-size 512kB --num-cpus 4 --disk-image $DISK_PATH
>>> --kernel $KERNEL_PATH --cpu-type $CPU_TYPE --script=$SCRIPT_PATH
>>> --l2_size=1MB --take-checkpoints=1,2
>>>
>>> warn: iobus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: bridge.master is deprecated. `master` is now called `mem_side_port`
>>> warn: membus.master is deprecated. `master` is now called
>>> `mem_side_ports`
>>> warn: bridge.slave is deprecated. `slave` is now called `cpu_side_port`
>>> warn: iobus.master is deprecated. `master` is now called `mem_side_ports`
>>> warn: apicbridge.slave is deprecated. `slave` is now called
>>> `cpu_side_port`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`

[gem5-users] Re: Is it ok to remove `maxRoutingTableSizeCheck`?

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Emil,

You can remove that check. However, you should note that the classic caches
aren't designed to support high-bandwidth operation. Also, this assert
triggering could be a sign that there's infinite queuing somewhere (which
is one reason why the classic caches aren't great for high bandwidth
systems).

Cheers,
Jason

On Wed, Sep 8, 2021 at 3:48 AM Emil VATAI via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> We are trying to do some simulations. We are using a simulator based on an
> old version of Gem5 ([1] created to simulate a64fx chip).
> We made some further modifications, namely replaced `SnoopMask` to be of
> type `std::bitset<>` to be able to run more-or-less arbitrary number of
> cores. And running with more cores resulted in triggering the following
> panic in `coherent_xbar.cc` (it occurs 2x in the code, around line 330 and
> 400 [3], not sure which one was triggered).
> ```
> panic_if(routeTo.size() > 512, "Routing table exceeds 512 packets\n");
> ```
> comparing this to a more recent version of gem5 the constant 512 seems to
> be the `maxRoutingTableSizeCheck` variable [4].
>
> My question is, how important is that check? How will it impact the
> simulation? Will it still be a "correct" simulation (or will skipping that
> check do something silly, like skip simulation half of the memory writes or
> something like that).
>
> Best,
> Emil
>
> [1] https://github.com/RIKEN-RCCS/riken_simulator
> [2] https://github.com/bgerofi/riken_simulator/
> [3]
> https://github.com/bgerofi/riken_simulator/blob/1f6627cf95688c508b73c8ead6838aa1f843f436/src/mem/coherent_xbar.cc#L339
> [4]
> https://github.com/gem5/gem5/blob/87c121fd954ea5a6e6b0760d693a2e744c2200de/src/mem/coherent_xbar.cc#L346
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[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Sam,

Sorry for the frustration. Writing better documentation is always #2 on the
priority list :(.

I always tell people not to trust any of the "options" to fs.py and se.py.
Those scripts have gotten so far beyond "out of hand" at this point that
they are almost useless. They are trying to be everything to everyone, and
they end up just being a mess of spaghetti code and confusion.

To take a checkpoint, you can add the following code to a python runscript:

m5.simulate(1)
m5.checkpoint()
m5.simulate(2)
m5.checkpoint()

I tested the above code by adding it to the
configs/learning_gem5/part1/two_level.py file.

*Maybe* this is what --take-checkpoints is doing. It's certainly what it
was *supposed* to do, but again, since this code has gotten so out of hand,
who knows if it's actually doing what it advertises.

If you want to use the m5ops to checkpoint, the code would look
something like the following (this isn't tested and it's off the top of my
head).

while 1:
  exit_event = m5.simulate()
  if exit_event.getCause() == 'checkpoint'):
m5.checkpoint(m5.outdir + '/' + str(num))
  else:
break

To restore from a checkpoint, pass the checkpoint directory as the only
parameter to m5.instantiate(ckpt_dir=).

Hope this helps! If you're still experiencing a hang in this case, it's
probably a bug in the drain() code somewhere. You can try to use one of the
drain debug flags (I don't know exactly what these are... check gem5
--debug-help for a list of debug flags). Making the python runscript do
exactly what you expect will also help with debugging. When you control the
script, adding prints is easy, too!

Finally, the file src/python/m5/simulate.py may be helpful to figure out
what's going on when instantiating, simulating, checkpointing, etc.

Cheers,
Jason

On Wed, Sep 8, 2021 at 6:14 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> Just to follow up, because I can see that there have been some issues with
> not including all of the requisite issues in other threads, here is the
> full output from what I described above.
>
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.1.0.0
> gem5 compiled Sep  7 2021 19:28:16
> gem5 started Sep  8 2021 09:09:11
> gem5 executing on sam-Precision-Tower-5810, pid 445665
> command line: build/X86/gem5.opt -d $CURR_DIR/debug
> $CURR_DIR/configs/example/fs.py --caches --l2cache --mem-type DDR3_1600_8x8
> --mem-size 2GB --meta-size 512kB --num-cpus 4 --disk-image $DISK_PATH
> --kernel $KERNEL_PATH --cpu-type $CPU_TYPE --script=$SCRIPT_PATH
> --l2_size=1MB --take-checkpoints=1,2
>
> warn: iobus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: bridge.master is deprecated. `master` is now called `mem_side_port`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: bridge.slave is deprecated. `slave` is now called `cpu_side_port`
> warn: iobus.master is deprecated. `master` is now called `mem_side_ports`
> warn: apicbridge.slave is deprecated. `slave` is now called `cpu_side_port`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: apicbridge.master is deprecated. `master` is now called
> `mem_side_port`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: iobus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: tol2bus.slave 

[gem5-users] Re: Query: Valgrind speed in FS

2021-09-07 Thread Jason Lowe-Power via gem5-users
Hi Sindhuja,

Yes, there is an expectation that valgrind causes a slowdown. Let me give
you a couple of suggestions.

1. Make sure you compile without tcmalloc (e.g., scons
build//gem5.opt --without-tcmalloc). Using tcmalloc will make
valgrind miss all allocations.
2. Use the suppressions file in util/valgrind-suppressions. This will hide
most of the python "errors". It was recently updated to suppress many more
errors that aren't really errors.

That said, I've had some recent problems myself with valgrind and the new
suppressions file being *very* slow. I think this is something we need to
look into. If you have any ideas on how to improve the performance, we
would appreciate hearing them! Otherwise, I guess we'll all just have to
keep waiting overnight ;)

Cheers,
Jason

On Tue, Sep 7, 2021 at 2:20 PM Sindhuja Gopalakrishnan Elango via
gem5-users  wrote:

> Hi Community,
>
> I ran into bad_alloc issues in GEM5 with the full system simulation of
> SPEC 2006 benchmarks.
>
> Suspecting a memory leak, I wanted to use valgrind to understand better.
>
>
>
> Without valgrind option, it takes less than 10 minutes for kernel to boot
> and also run the 400.perlbench/attrs benchmark.
>
> But with valgrind, it has crossed 2 hrs and the kernel hasn’t yet booted.
>
>
>
> Usage:
>
> valgrind --log-file=attrs.val.txt --error-limit=no   $GEM5_CMD
>
>
>
> I would like to know if this slowdown is reasonable with valgrind?
>
> And do you have any suggestions for a memory leak detection tool that is
> faster than valgrind and works well with gem5?
>
>
>
> Appreciate your time and effort. Thanks much.
>
>
>
> Best Regards
>
> Sindhuja
>
>
>
>
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[gem5-users] Re: regarding building of dependencies

2021-09-02 Thread Jason Lowe-Power via gem5-users
Hello,

It should be X86 (capitol X) instead of x86. You can see the files in
gem5/build_opts for the different possibilities for default build variables.

Cheers,
Jason

On Thu, Sep 2, 2021 at 3:58 AM Sravani Sravanam 20PHD7041 via gem5-users <
gem5-users@gem5.org> wrote:

>  sir,
> i am sravani sravanam a research scholar in vit ap university.while
> running at initial stage like
> scons build/x86/gem5.opt -j2 i am getting an error like this
> Error: Cannot find variables file
> /home/hp/Desktop/srav/gem5/build/variables/x86
>or default file(s) /home/hp/Desktop/srav/gem5/build_opts/x86.
> please help me
> thanking you
> sravani sravanam
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[gem5-users] Re: Collecting Two Sets of Data Within Same Simulation

2021-08-13 Thread Jason Lowe-Power via gem5-users
Hi Sam,

This is a use case that I don't think we've thought about in the mainline
gem5. I think the easiest solution would be to add some custom Statistics
objects to track the info from the function you're interested in.

Cheers,
Jason

On Wed, Aug 11, 2021 at 10:59 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I'm currently running a full system simulation, and would like to collect
> statistics from one particular function as well as overall statistics from
> the simulation. Unfortunately, the function gets called many times, so
> simply dumping stats at the beginning and end of the function makes the
> resulting stats file too large to do any analysis on.
>
> Is there an easy way to get around this issue?
>
> Thank you for your help!
>
> Best,
> Sam
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[gem5-users] Re: 答复: gem5 v21.1 released!

2021-07-29 Thread Jason Lowe-Power via gem5-users
Hi Liyichao,

We welcome contributions to the gem5 resources! Currently, we have full
system resources available for x86 and one available for RISC-V. We don't
have any Arm resources available right now, but that's only because we
haven't had the time (or resources ;)) to get around to it. Again, we
welcome contributions, though!

Cheers,
Jason

On Wed, Jul 28, 2021 at 6:24 PM Liyichao via gem5-users 
wrote:

> Hi Bruce:
>
>  I see the GEM5 resource mentioned on the GEM5 official website.
> Are all the resources provided in the GEM5 resource based on x86? For
> example, SPEC2017, are there AARCH64-based versions available for these
> resources?
>
>
>
> Best regards,
>
> Liyichao
>
>
>
>
>
> *发件人:* Bobby Bruce via gem5-users [mailto:gem5-users@gem5.org]
> *发送时间:* 2021年7月29日 8:51
> *收件人:* gem5 Developer List ; gem5 users mailing list <
> gem5-users@gem5.org>; gem5-annou...@gem5.org
> *抄送:* Bobby Bruce 
> *主题:* [gem5-users] gem5 v21.1 released!
>
>
>
> Dear all,
>
>
>
> gem5 v21.1.0.0 has officially been released.
>
>
>
> You can use  `git clone https://gem5.googlesource.com/public/gem5`
>  to obtain the latest release
> and consult the RELEASE-NOTES.md for a high-level overview of significant
> changes:
> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md
>
>
>
> A special thank you to all our contributors for making this possible. We
> had 780 commits from 48 unique contributors over the past few months. It's
> quite an achievement. We look forward to your continued support in our
> v21.2 release!
>
>
>
> Kind regards,
>
> Bobby
>
> --
>
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
>
>
> web: https://www.bobbybruce.net
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[gem5-users] Re: ARM KVM

2021-07-12 Thread Jason Lowe-Power via gem5-users
To use hardware-accelerated virtualization (i.e., KVM) your host and guest
must have the same ISA (and the host must have virtualization extension).

Cheers,
Jason

On Mon, Jul 12, 2021 at 12:17 PM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 community,
>
> I have installed the latest gem5 on an x86 machine. Is it possible to
> run ARM FS with kvm on X86 machine or the host machine must be
> ARM-based?
>
> I try to execute the following configuration (from this thread
> https://www.mail-archive.com/gem5-users@gem5.org/msg19472.html):
>
> $GEM5/build/ARM/gem5.opt $GEM5/configs/example/arm/fs_bigLITTLE.py
> --kernel=vmlinux.arm64 --machine-type VExpress_GEM5 --disk
> ubuntu-18.04-arm64-docker.img --cpu-type kvm --big-cpus 4
>
> and I get the following error (which means that there is not the kvm
> option):
>
> fs_bigLITTLE.py: error: argument --cpu-type: invalid choice: 'kvm'
> (choose from 'atomic', 'timing', 'exynos')
>
> May you help me, please?
>
> Best regards,
> Nikos
>
>
>
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[gem5-users] Re: Custom SimObject Causes Host Machine to Freeze

2021-07-06 Thread Jason Lowe-Power via gem5-users
Hi Sam,

My suggestion would be to use gdb. You can run gem5 in gdb and then use
ctrl-c to stop the execution and see where the program is getting stuck.
Also, enabling debug flags (or just good ole printf debugging) can also be
useful in these cases.

Another option with gdb would be to put breakpoints on each of the
functions in your object (e.g., the constructor) and then step through to
see what's happening.

A final thought... does your object enqueue any events? If so, are the
enqueued *in the future*? If you enqueue an event at the current tick
(curTick()) and then that event enqueues an event at the current tick you
can get stuck in an infinite loop. (The Event debug flag could be useful
here, too.)

Cheers,
Jason

On Tue, Jul 6, 2021 at 8:56 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I'm writing because I'm working with a custom SimObject that I wrote that
> seems to crash my host machine. I know it's this particular SimObject
> because the script works as expected when run without the object, but it
> makes debugging an excruciatingly difficult process.
>
> Is this an issue that anyone has seen before? And if so, does anyone have
> any hints as to what might be causing the host to crash?
>
> Thank you for your help!
>
> Best,
> Sam
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[gem5-users] Re: question about RSCV-V implementation on Gem5

2021-07-05 Thread Jason Lowe-Power via gem5-users
See https://gem5.atlassian.net/browse/GEM5-618

On Sat, Jul 3, 2021 at 5:23 PM lovline via gem5-users 
wrote:

> Hi,
>We are working on an important project, and we want to use RSCV-V1.0
> vector instructions on Gem5.
>But we cann't find any features or codes about RSCV-V on Gem5.
>We searched the mail-list also did not find the plan for RSCV-V1.0.
>So we send this mail.
>Please help us, thank you very much.
>
>
> Regards,
> Will
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[gem5-users] Re: does gem5 have a C++ API?

2021-07-02 Thread Jason Lowe-Power via gem5-users
Hello,

Unfortunately, I don't think gem5 is the right tool for this job. When you
run that command, gem5's embedded python interpreter is executing `se.py`.
There's not really a way to easily get around this. You could try to
compile gem5 without python (--without-python, IIRC), but then configuring
the system you're running is difficult, if not impossible, depending on the
system you want to simulate.

Cheers,
Jason

On Thu, Jul 1, 2021 at 6:06 PM Konstantin Serebryany <
konstantin.s.serebry...@gmail.com> wrote:

> Hi Jason,
>
> Thanks for the reply!
> I was hoping for something light-weight, similar to Unicorn, but based on
> gem5 instead of QEMU...
>
> I tried running
>   build/X86/gem5.opt configs/example/se.py -c
> ./tests/test-progs/hello/bin/x86/linux/hello
> and it takes 0.3 second -- too slow.
>
> The profile shows:
>   14.55%  gem5.opt  libpython3.9.so.1.0[.] _PyEval_EvalFrameDefault
>
>
>
>2.31%  gem5.opt  libpython3.9.so.1.0[.] _PyType_Lookup
>
>
>
>2.01%  gem5.opt  libpython3.9.so.1.0[.]
> _PyObject_GenericGetAttrWithDict
>
>
>1.09%  gem5.opt  libpython3.9.so.1.0[.] _Py_CheckFunctionResult
>
>
>
>1.06%  gem5.opt  libpython3.9.so.1.0[.] 0x002000b0
>
>
>
> ...
> I.e. all the time for simulating a tiny test is spent in python.
>
> I'd like to be able to simulate tiny programs, like "hello" from the
> examples,
> but hopefully at least 100x faster than this.
>
> What's the best supported mechanism for running many tiny simulations
> w/o having to pay for the large python overhead?
> Any examples?
>
> --kcc
>
>
>
>
>
>
> On Thu, Jul 1, 2021 at 5:00 PM Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> It's somewhat possible. You can compile gem5 as a library (e.g., scons
>> build//libgem5-opt.so). However, gem5 *is a python
>> interpreter* and is configured via python scripts. Getting that to work
>> with an external program is "exciting". It's possible to get python
>> working, and there are other workarounds like using the CXXConfig
>> interface, but it's not straightforward or easy to understand.
>>
>> Unless you're trying to integrate gem5 into another simulator, it's
>> unlikely that invoking gem5 from another program is the best option. Even
>> in this case, I would advise going the other way and using gem5 as the
>> driver simulator. That said, there are many simulators that integrate with
>> gem5. You can easily hook in things like DRAMSim, at one point I integrated
>> it with GPGPU-Sim (this is now incredibly out of date), and there is an
>> SST-gem5 bridge that we are actively working on. Finally, there are many
>> efforts to integrate gem5 with SystemC including implementing the entire
>> SystemC spec in gem5.
>>
>> Hopefully this helps. I'd be happy to provide more specific help with
>> some more information :).
>>
>> Cheers,
>> Jason
>>
>> On Thu, Jul 1, 2021 at 4:49 PM Konstantin Serebryany via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,
>>>
>>> [gem5 newbie here... ]
>>>
>>> Does gem5 have a C++ API?
>>>
>>> I am interested in using gem5 as a library, i.e. invoking
>>> the system call emulation mode from within my process,
>>> without fork/exec or python.
>>> Is that at all possible?
>>> Any pointers?
>>>
>>> thanks!
>>>
>>> --kcc
>>>
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>>
>>
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[gem5-users] Re: does gem5 have a C++ API?

2021-07-01 Thread Jason Lowe-Power via gem5-users
Hello,

It's somewhat possible. You can compile gem5 as a library (e.g., scons
build//libgem5-opt.so). However, gem5 *is a python
interpreter* and is configured via python scripts. Getting that to work
with an external program is "exciting". It's possible to get python
working, and there are other workarounds like using the CXXConfig
interface, but it's not straightforward or easy to understand.

Unless you're trying to integrate gem5 into another simulator, it's
unlikely that invoking gem5 from another program is the best option. Even
in this case, I would advise going the other way and using gem5 as the
driver simulator. That said, there are many simulators that integrate with
gem5. You can easily hook in things like DRAMSim, at one point I integrated
it with GPGPU-Sim (this is now incredibly out of date), and there is an
SST-gem5 bridge that we are actively working on. Finally, there are many
efforts to integrate gem5 with SystemC including implementing the entire
SystemC spec in gem5.

Hopefully this helps. I'd be happy to provide more specific help with some
more information :).

Cheers,
Jason

On Thu, Jul 1, 2021 at 4:49 PM Konstantin Serebryany via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> [gem5 newbie here... ]
>
> Does gem5 have a C++ API?
>
> I am interested in using gem5 as a library, i.e. invoking
> the system call emulation mode from within my process,
> without fork/exec or python.
> Is that at all possible?
> Any pointers?
>
> thanks!
>
> --kcc
>
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[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian,

The AMD GPU model has never been tested with Arm. I doubt the ROCm stack
will compile/work with any ISA other than x86, unfortunately.

For multi-GPU support see
http://www.gem5.org/2020/05/30/enabling-multi-gpu.html

Of course, multiple CPUs will work with no problem with or without GPU(s).

Cheers,
Jason

On Wed, Jun 30, 2021 at 8:05 AM adrian via gem5-users 
wrote:

> Hi Jason,
>
> Thanks a lot for this useful information.
> Is it possible to have several CPUs + several GPUs running in parallel?
> I'm using Arm as the CPU's ISA. I don't know how this GPU ISA deals with
> other ISAs.
>
> Sincerely,
> Adrián
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[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian,

gem5 has support for AMD's GCN3 (compute) GPU in SE mode, and we're working
on merging both Vega support (AMD's newer GPU ISA) and full system support.
The status of these new features can be followed on Jira.

Here's documentation on the current GPU support:
http://www.gem5.org/documentation/general_docs/gpu_models/GCN3
http://www.gem5.org/2020/05/27/modern-gpu-applications.html

Also, there are a number of resources to help you get started. For instance:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/hip-samples/
https://resources.gem5.org/resources/dnn-mark (available soon, as in about
15 minutes after I send this email)

Cheers,
Jason

On Wed, Jun 30, 2021 at 7:05 AM adrian via gem5-users 
wrote:

> Hi,
>
> I am interested in simulating a GPU in gem5. Just by googling I discovered
> a repo from 2017 but I've also seen gem5 v21 has some files regarding to
> the GPU.
> Could you please confirm gem5 v21 supports a GPU model? There is not much
> info about it on internet. How can this GPU model be used?
>
> Many thanks,
> Sincerely,
> Adrián
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[gem5-users] Re: Fatal error while running multithreaded program in SE mode

2021-06-25 Thread Jason Lowe-Power via gem5-users
What version of gem5 are you using? I believe gem5-20.0+ has the getdents
syscall implemented. I'm sure that 21.0 has the syscall implemented.
Whether you're using Ruby or classic caches it shouldn't make
any difference on whether the syscalls are implemented.

Cheers,
Jason

On Fri, Jun 25, 2021 at 3:32 AM hissa alshamsi via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
>
>
>
> I am trying to run a multithreaded program in SE mode, after installing
> m5thread and following the steps in
> https://github.com/WeijingShi/playground/blob/master/Run-openmp-code-in-gem5.md
>
>
>
> But I keep getting that syscall getdents unimplemented.
>
>
>
> This is the line I have used:
>
> build/X86/gem5.opt configs/example/se.py --cpu-type=TimingSimpleCPU
> –cpu-cycle=2GH-n 8 --cmd=m5threads/tests/test_omp -o '8 8'
>
>
>
>
>
>  REAL SIMULATION 
>
> info: Entering event queue @ 0.  Starting simulation...
>
> warn: Attempting to open special file: /sys/devices/system/cpu. Ignoring.
> Simulation may take un-expected code path or be non-deterministic until
> proper handling is implemented.
>
> fatal: syscall getdents (#78) unimplemented.
>
> Memory Usage: 829528 Kbytes
>
>
>
> Any clue on how to run a multithreaded program in SE mode without using
> ruby?
>
>
>
> Thank you in advance,
>
> Hessa.
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[gem5-users] Re: gem5 RISCV, issue on boot when mounting filesystem

2021-06-25 Thread Jason Lowe-Power via gem5-users
Hi everyone,

These details on gem5-resources have also been tested multiple times. We
have also gotten unmodified OpenSBI working with gem5 as well. Ayaz can
provide more details if you need.

https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/riscv-fs/

Cheers,
Jason

On Fri, Jun 25, 2021 at 8:22 AM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:

> Dear David,
>
> I have used the bbl, Linux Kernel, and riscv_disk from the following
> GitHub: https://github.com/ppeetteerrs/gem5-RISC-V-FS-Linux/ .You can
> use either the files from prebuild directory or you can create your
> own according to instructions of this Github. Specifically, I have
> used the following configurations which are working properly (5 of 6):
>
>  RISCV 1 core 
>
> AtomicSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=AtomicSimpleCPU
> --disk-image=$OUT/riscv_disk -n 1
>
>
> TimingSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=TimingSimpleCPU
> --disk-image=$OUT/riscv_disk -n 1
>
> DerivO3CPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=DerivO3CPU
> --disk-image=$OUT/riscv_disk -n 1
>
>
>  RISCV 2 cores 
>
> AtomicSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=AtomicSimpleCPU
> --disk-image=$OUT/riscv_disk -n 2
>
> TimingSimpleCPU (Working)
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=TimingSimpleCPU
> --disk-image=$OUT/riscv_disk -n 2
>
> DerivO3CPU (NOT Working): void BaseDynInst< 
>  >::initVars() [with Impl = O3CPUImpl]: Assertion `cpu->instcount <=
> 1500' failed.
>
> $GEM5/build/RISCV/gem5.opt -d $GEM5/node0
> $GEM5/configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
> --mem-size=512MB --mem-type=DDR4_2400_8x8 --cpu-type=DerivO3CPU
> --disk-image=$OUT/riscv_disk -n 2
>
>
> To be noticed that when I use --mem-size more than 512MB, gem5 is not
> booted.
>
>
> Finally, when I use the last configuration I get the above error
> (please let me know if you/anyone can resolve it :))
>
> Best regards,
> Nikolaos Tampouratzis
>
>
> Quoting Truan David via gem5-users :
>
> > Hello,
> > We are a team working on gem5 RISCV. We are trying to use gem5
> > full-system but we are encountering some issues when mounting the
> > rootfs/initramfs.
> >
> > This is our setup:
> > - gem5 on branch develop from
> > https://gem5.googlesource.com/public/gem5 (c493d2c4ad)
> > - BBL on branche master from https://github.com/riscv/riscv-pk.git
> (e8e6b3aa)
> > - Linux 5.10, checkout on v5.10 tag (2c85ebc57)
> >
> > This is what we tried so far:
> >
> > -Compiling BBL with and without specifying the DTS: No changes
> > -Compiling BBL with Linux vmlinux OR Image as payload: No changes
> > -Compiling Linux with an minimalistic initramfs which only prints a
> > "Hello World" from the init script: No changes
> > -Using fs_linux.py OR run_riscv.py as the entry point: No changes
> >
> > Here are the boot logs from different experiments, with only the
> > last lines of the boot log to keep this mail short:
> >
> > =
> > This is the boot log when specifying a disk-image param, using
> fs_linux.py:
> >
> > Command:
> > $GEM5_FAST_BIN -v \
> > -d $GEM5_OUTPUT \
> > $GEM5_HOME/configs/example/riscv/fs_linux.py \
> > --cpu-type=AtomicSimpleCPU \
> > --cpu-clock=1GHz \
> > -n 1 \
> > --disk-image=$DISK \
> > --kernel= \
> > --mem-type=DDR4_2400_4x16 \
> > --mem-size=4GB \
> > --command-line="root=/dev/vda ro console=ttyS0"
> >
> >
> >  m5 terminal: Terminal 0 
> > ...
> > [1.123014] [drm] radeon kernel modesetting enabled.
> > [1.146199] loop: module loaded
> > [1.147219] virtio_blk virtio0: [vda] 6821 512-byte logical
> > blocks (3.49 MB/3.33 MiB)
> > [1.147423] vda: detected capacity change from 0 to 3492352
> >
> > =
> > This is the boot log when NOT specifying a disk-image param, using
> > fs_linux.py:
> >
> > Command:
> > $GEM5_FAST_BIN -v \
> > -d $GEM5_OUTPUT \
> > $GEM5_HOME/configs/example/riscv/fs_linux.py \
> > --cpu-type=AtomicSimpleCPU \
> > --cpu-clock=1GHz \
> > -n 1 \
> > --kernel= \
> > --mem-type=DDR4_2400_4x16 \
> > --mem-size=4GB \
> > --command-line="root=/dev/vda ro console=ttyS0"
> >
> >  m5 terminal: Terminal 0 
> > ...
> > [1.121246] [drm] radeon kernel modesetting enabled.
> > [1.144593] loop: 

[gem5-users] Re: Understanding write timing in MemCtrl

2021-06-22 Thread Jason Lowe-Power via gem5-users
Hi Vincent,

It depends on when/how you're ending the simulation. If you end the
simulation at some particular tick, then you'll see writes left in the
write queue. Just like a real machine, writes don't happen instantaneously,
and at some point in time, there are writes sitting in the write buffer
(and dirty data in the cache, too). In gem5, like a real system, if you
wanted to ensure everything is flushed to persistent storage, you could
call a flush system call. Also like a real system, there is no instruction
to flush the memory controller write queues. The data there is
architecturally visible, so it doesn't matter if it's in the write queue or
in memory.

If for some reason you really need all of the data in gem5's backing memory
(e.g., to take a checkpoint), you can call the drain() function which will
dump everything.

I believe you're really asking about timing accuracy, though. If that's the
case, I would give you two comments: (1) I would expect that your program
runs long enough that 32 cache lines that haven't been written back to
memory will make no difference in the overall execution time. And (2) if
you really need to be modeling that this detailed of a level, you should
probably be using full system mode so you can correctly model syscalls, etc.

Hopefully this answers your question!

Cheers,
Jason

On Tue, Jun 22, 2021 at 8:06 AM Vincent R. via gem5-users <
gem5-users@gem5.org> wrote:

> Hi again,
>
> just wanted to give this a second try. No urgent matter here, just some
> lack of understanding and curiosity on my side.
>
> Thank you,
> Vincent
>
>
> Am 04.06.2021 um 11:34 schrieb Vincent R.:
> > Hi everyone,
> >
> > I am currently doing some experiments with packet timings in the
> > Memory Controller( gem5 version 20.1.0.2., SE mode). As I understood
> > it, writes accesses are serviced instantly by the controller and their
> > actual timing is only calculated later when the corresponding
> > nextReqEvent is processed and the packet is removed from the write queue.
> > This works fine, however, with default parameters set, there are still
> > a lot of write packets left in the queue, when the simulation exits.
> > So, in my understanding, these are never correctly timed.
> >
> > As I was experimenting I set the write threshold parameters of MemCtrl
> > in a way to force the controller to process all writes. Naturally the
> > run time increases by a large amount of ticks.
> >
> > My question: How does gem5 perform a correct timing simulation while
> > leaving untimed writes in the queue at the end of simulation? Or
> > doesn't it? Have I misunderstood something?
> >
> > Test system is a simple example configuration without caches.
> >
> >
> > Thank you for your help.
> > Vincent
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[gem5-users] Re: Memory-Intensive C Programs in SE Mode

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Sam,

Are the (virtual, physical?) addresses different when you use the larger
arrays? I wonder if the underlying mmap or malloc calls are breaking in SE
mode somehow. Maybe, after you allocate in your guest code you can print
out the virtual address to make sure it looks reasonable. You can also use
a debug flag to print out the virtual->physical mapping that gem5 assigns
in the syscall_emul file, IIRC. That's where I would start.

Cheers,
Jason

On Thu, Jun 17, 2021 at 6:50 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I'm writing because I'm trying to run a relatively simple, but
> memory-intensive C microbenchmark in SE mode. In particular, it allocates
> and randomly fills a 2MB array, then performs *n* random accesses to the
> array and increments the value.
>
> The program outputs that it is increasing the stack size by a page ("info:
> Increasing stack size by one page."), and eventually no more output is
> produced. I tried putting some sanity check code in the LLC logic (i.e.,
> print "Hello, does this work" every 10,000 accesses), and it seems as
> though the system has actually stopped executing.
>
> What's weird about this is that the program works for smaller arrays, such
> as 10kB, but those are somewhat uninteresting for my work. I suspect I'll
> have to turn to full system mode, but ideally I'd like to work with a
> simpler architecture.
>
> Is there any reason why this might be the case?
>
> Thank you for your help!
>
> Best,
> Sam
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[gem5-users] Re: Reserve a chuck of memory space in SE mode

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Xijing,

You can set specific mappings from virtual to physical addresses by calling
the `map()` function on the Process object from your python configuration
file. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/Process.py#37

Then, once you have a virtual->physical mapping set, you can use mmap() in
your guest application and allocate memory at a specific virtual address.
Then, when you read/write that virtual address it will be translated to the
physical address you set in your config file and you can do whatever you
want with the address in the simulator.

Cheers,
Jason

On Sat, Jun 19, 2021 at 1:10 PM Xijing Han via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> I want to reserve a chunk of memory space for other usage so that the
> application won't use it. How can I achieve this in SE mode?
>
> Thanks,
> Xijing Han
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[gem5-users] Re: Call m5ops writefile when simulation ends

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Pedro,

No, I don't think there's an easy way to run m5_write_file on the guest
from the host. That is an instruction that is executed on the guest, and
the host can't easily control what is executing on the guest (especially
when you consider that it has to execute in the right context, etc.).
Similarly, the host doesn't have any (easy) way of knowing what address or
location on the disk to read/write.

I'm sure you could devise a way to do this, but it's not going to be
straightforward :). I would do what you suggest and just use stdout via the
serial tty.

Cheers,
Jason

On Wed, Jun 16, 2021 at 6:52 AM Pedro Becker via gem5-users <
gem5-users@gem5.org> wrote:

> Hello gem5 community,
>
> I'm running an application with FS (fs.py), for which I have generated
> some checkpoints.
> Now I can restore the checkpoints and run for a given number of ticks. All
> good.
>
> My application outputs data to a file as the execution goes on. This file
> is written in the image, inside gem5.
> Now, I'd like to have the generated file in the host once the simulation
> finishes.
>
> I know that there is the m5op 'm5_write_file', which can 'export' the file
> from the simulated image to the host.
> However, since my simulation ends abruptly (after a number of ticks), I
> cannot make sure I call the m5op to export the file at the very last moment
> (collecting the maximum amount of data produced by my program).
>
> Is there a simple way to request this file transfer from the python
> scripts (e.g., fs.py), once I leave the simulation loop (i.e., when the
> simulation ends)?
> The alternative would be to output the log to the screen (together with
> other info already printed there) and filter the output later, which is
> what I'm going to do in the lack of a more elegant way.
>
> Again,
> Thank you.
> ___
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[gem5-users] Re: Making virtual address range of a PIO device uncacheable in x86 FS simulation.

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Deepak,

Yeah, the cache disable bit may not work correctly in the page table
walker/TLB. You can check the code there to see if that's what's going
wrong.

You can also try adding an E820 entry to the workload object (e.g.,
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/system.py#305)
which marks that physical range as uncachable. I believe that works
correctly.

Cheers,
Jason

On Thu, Jun 17, 2021 at 4:02 AM Deepak Mohan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>   I'm doing some experiments using gem5 FS mode for x86.
> In the FS mode I'm running a custom OS written for the requirements of
> my experiment. I have added a PIO device to the x86 system which
> responds to reads and writes to an address range. In the OS I have
> mapped this device to a range in the PCI memory map region (@3GB). I
> don't want this range to be cached, but when I add the cache hierarchy
> to my FS simulation it seems that the device range is also cached. I
> tried setting the C bit (Cache disable) in page table entries to
> prevent this device range from getting cached, but it seems that
> doesn't work. What can I do to prevent the address range of my device
> from being cached , or am I doing something conceptually wrong ? Any
> ideas / suggestions / pointers would be helpful.
>
> Thanks,
> Deepak Mohan.
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[gem5-users] Re: [gem5 version 20.1.0.5] Writing to satp in RISCV FS mode causes error when L1 caches are added.

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Deepak,

Have you tried the latest gem5? There's been a lot of work in both
gem5-21.0 and on gem5-develop to improve the RISC-V FS support. Another
option would be to look at how the RISC-V code has changed to see if that
helps diagnose this problem.

Cheers,
Jason

On Fri, Jun 18, 2021 at 10:29 AM Deepak Mohan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>  I'm working on an older version of gem5 (20.1.0.5), in which I run a
> RISCV full system simulation, I have added a minimal platform in this
> version of gem5 to run the FS simulation, but when I add cache
> hierarchy to the simulation the following error occurs after writing
> to the satp CSR.
>
> void Packet::setCacheResponding():
> Assertion`!flags.isSet(CACHE_RESPONDING)' failed.
>
> I'm able to switch address spaces by writing to satp CSR when there is
> no cache hierarchy.
>
> Has anyone faced similar problems ?, any pointers/directions would be
> appreciated
>
> Thanks,
> Deepak Mohan
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[gem5-users] Re: Queued Ports

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Sam,

No, there's not good documentation on this (yet ;)). It's relatively easy
to set up, though. Instead of using a single packet ptr, you can have a
queue (or whatever datastructure you would like), and you can set the
blocked flag only when it is "full" (e.g., the number of items in the
structure is equal to the max size you want to model.

I would caution you against using the `QueuedPort` object in gem5, though.
This creates an infinite queue by default, and it difficult to use in a way
that models something reasonable. That said, the `PacketQueue` object may
come in handy.

Cheers,
Jason

On Fri, Jun 18, 2021 at 12:07 PM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> Is there documentation for a conventional way to set up queued ports in
> custom memory objects? In learning_gem5, there is really good documentation
> for blocking ports, but the blocking port is currently a bottleneck in my
> application.
>
> Thank you in advance!
>
> Best,
> Sam
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[gem5-users] Re: Caches with different line sizes

2021-06-08 Thread Jason Lowe-Power via gem5-users
Hi Patrick,

gem5 doesn't support multiple cache line sizes "out of the box", but
there's no reason you couldn't add the support. Creating a memory-side
cache with a larger cache line is certainly possible! You might need to
make some modifications to the Cache SimObject or create your own object.
If you're using Ruby, this would be a protocol modification, but, again,
it's absolutely possible.

Cheers,
Jason

On Tue, Jun 8, 2021 at 10:22 AM Patrick Sheridan (psheridan) via gem5-users
 wrote:

> Micron Confidential
>
> Does gem5 support having multiple cache line sizes (e.g. a non-coherent
> cache, below the point of coherence, having a larger line size)?
>
>
>
> Regards,
>
> Patrick
>
> Micron Confidential
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[gem5-users] Re: gem5.org seems to be down

2021-06-08 Thread Jason Lowe-Power via gem5-users
It seems to be back now, but please let us know if you can't access it!

I think it was related to the Fastly outage. See the CNN article for more
details :).

https://www.cnn.com/2021/06/08/tech/internet-outage-fastly/index.html

Cheers,
Jason

On Tue, Jun 8, 2021 at 3:21 AM Pedro Henrique Exenberger Becker via
gem5-users  wrote:

> I'm experiencing this as well.
> Apparently, it is not just for us:
> https://downforeveryoneorjustme.com/gem5.org
>
> Best,
> Pedro.
>
> Em ter., 8 de jun. de 2021 às 12:07, Rajesh S via gem5-users <
> gem5-users@gem5.org> escreveu:
>
>> Hi,
>>
>> I was looking around in the documentation and I noticed that gem5.org
>> has been down since a while. Are others facing this too?
>>
>> Thanks,
>> Rajesh Shashi Kumar
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[gem5-users] Re: Topology errors

2021-05-28 Thread Jason Lowe-Power via gem5-users
Hi Travix,

I believe Garnet (and/or Ruby) can only support 64 cores. They use a 64 bit
number as a mask for the cores. To fix this, we'll need to dig in and
replace all of those explicitly sized variables with vector. I don't
think it's actually that many plance that need to change, but it's been a
while since I've looked into it.

The _intlv_match (interleaving bits match) may be a different problem. This
could be caused by trying to use the wrong bits to interleave the directory
addresses. I would carefully check the config file you're using to dig into
how the addresses are being interleaved at either the L2 and/or directory
levels.

Generally, gem5 hasn't been used much with core counts above 64, so, there
may be a number of bugs that are exposed. We would appreciate contributions
to help us improve things!

Cheers,
Jason

On Thu, May 27, 2021 at 5:31 PM Travis Dai via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all users,
>
>
>
> I have implemented a ring topology in gem5, it works well when set up
> nodes number = 64.
>
>
>
> When I set cpu =60, I met the following error: “fatal: fatal condition
> !masks.empty() && _intlv_match >= ULL(1) << masks.size() occurred: Match
> value 32 does not fit in 5 interleaving bits. Memory Usage: 149132 KBytes”
>
>
>
> When I set cpu =128/256, I met the following error: “fatal: Number of
> bits(64) < size specified(65). Increase the number of bits and recompile.
> Memory Usage: 856144 KBytes”
>
>
>
> Does anyone know the reason?
>
>
>
> Best,
>
> Travis
>
>
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[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

2021-05-12 Thread Jason Lowe-Power via gem5-users
Hmm... That's interesting. It could have something to do with the I/O hole
for x86 at 3-4GB. This is a huge pain for gem5's config scripts. We hack
around this in our config scripts (e.g., for gem5-resources). See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/npb/configs/system/system.py#59
for an example.

Those scripts have been tested with 8 cores and more than 4GB of memory
(maybe 64G?). We may also have run it with 32 cores, but I'm not sure if
that has been tested recently.

Cheers,
Jason

On Tue, May 11, 2021 at 8:03 PM Liyichao  wrote:

> Hi Jason:
>
>
>
>  I find that if I set –mem-size < 4GB, there is no error, but when
> I set –mem-size=4GB or more than 4GB, the error occurred.
>
>
>
>
>
>
>
> *发件人:* Liyichao
> *发送时间:* 2021年5月12日 0:26
> *收件人:* Jason Lowe-Power 
> *抄送:* gem5 users mailing list 
> *主题:* RE: [gem5-users] Fail to bootup with KVM in se.py on X86 arch
>
>
>
> Hi Jason:
>  I make two tests:
>
> 1. I write a test code follow "open /dev/kvm” "create vm” "create vcpu”
> ,it has no error;
>
> 2.  I put allocate pmem and create vcpu in create_vm function in gem5,
> not outside create_vm,it has no error.
>
>
>
> so I suspect if the allocate pmem function in gem5 source has any wrongs
> ?
>
> *发件人: *Jason Lowe-Power
>
> *收件人: *Liyichao
>
> *抄送: *gem5 users mailing list
>
> *主题: *Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch
>
> *时间: *2021-05-11 22:47:19
>
>
>
> Hello,
>
>
>
> I wonder if you have a maximum number of vcpus set on your host system.
> Otherwise, I can't think of any specific limitation to creating vcpus.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Tue, May 11, 2021 at 2:36 AM Liyichao  wrote:
>
> Hi Jason:
>
>
>
>  I use strace to follow the call stack, I find that the ioctl()
> with KVM_CREATE_VCPU returned EEXIST errno, this means the vCPU exist.
>
>
>
>ioctl(5, KVM_CREATE_VCPU, 2)= -1 EEXIST (File
> exists)
>
>
>
>
>
> *发件人:* Liyichao
> *发送时间:* 2021年5月11日 12:54
> *收件人:* 'Jason Lowe-Power' ; gem5 users mailing list <
> gem5-users@gem5.org>
> *主题:* 答复: [gem5-users] Fail to bootup with KVM in se.py on X86 arch
>
>
>
> Hi Jason:
>
>  I have add a DPRINTF in line 559 of vm.cc , it showed “  0:
> system.kvm_vm: *debug vcpuID is 0”
>
>
>
>  Any KVM use limitations in X86?
>
>
>
>
>
> gem5 version 21.0.0.0
>
> gem5 compiled May 11 2021 01:04:20
>
> gem5 started May 11 2021 01:09:26
>
> gem5 executing on ubuntu, pid 53534
>
> command line: ./build/X86/gem5.opt --debug-flags=Kvm configs/example/se.py
> --cpu-type=X86KvmCPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches
> --l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB
> --num-cpus=1 -I 5000 -c ./test
>
>
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> Global frequency set at 1 ticks per second
>
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (32768 Mbytes)
>
>   0: system.cpu: vcpuID is 0
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
>   0: system.cpu: ActivateContext 0
>
>  REAL SIMULATION 
>
>   0: system.kvm_vm: Mapping 1 memory region(s)
>
>   0: system.kvm_vm: Mapping region: 0x0x7f0b007b7000 -> 0x0 [size:
> 0x8]
>
>   0: system.kvm_vm: vmFD is 5, p1 is 140724538190576
>
>   0: system.cpu: charlie, vcpuID is 0
>
>   0: system.kvm_vm: vmFD is 5, p1 is 0
>
>   0: system.kvm_vm: *debug vcpuID is 0
>
> panic: KVM: Failed to create virtual CPU
>
> Memory Usage: 33838804 KBytes
>
> Program aborted at tick 0
>
> --- BEGIN LIBC BACKTRACE ---
>
> ./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x562

[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

2021-05-11 Thread Jason Lowe-Power via gem5-users
Hello,

I wonder if you have a maximum number of vcpus set on your host system.
Otherwise, I can't think of any specific limitation to creating vcpus.

Cheers,
Jason

On Tue, May 11, 2021 at 2:36 AM Liyichao  wrote:

> Hi Jason:
>
>
>
>  I use strace to follow the call stack, I find that the ioctl()
> with KVM_CREATE_VCPU returned EEXIST errno, this means the vCPU exist.
>
>
>
>ioctl(5, KVM_CREATE_VCPU, 2)= -1 EEXIST (File
> exists)
>
>
>
>
>
> *发件人:* Liyichao
> *发送时间:* 2021年5月11日 12:54
> *收件人:* 'Jason Lowe-Power' ; gem5 users mailing list <
> gem5-users@gem5.org>
> *主题:* 答复: [gem5-users] Fail to bootup with KVM in se.py on X86 arch
>
>
>
> Hi Jason:
>
>  I have add a DPRINTF in line 559 of vm.cc , it showed “  0:
> system.kvm_vm: *debug vcpuID is 0”
>
>
>
>  Any KVM use limitations in X86?
>
>
>
>
>
> gem5 version 21.0.0.0
>
> gem5 compiled May 11 2021 01:04:20
>
> gem5 started May 11 2021 01:09:26
>
> gem5 executing on ubuntu, pid 53534
>
> command line: ./build/X86/gem5.opt --debug-flags=Kvm configs/example/se.py
> --cpu-type=X86KvmCPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches
> --l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB
> --num-cpus=1 -I 5000 -c ./test
>
>
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> Global frequency set at 1 ticks per second
>
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (32768 Mbytes)
>
>   0: system.cpu: vcpuID is 0
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
>   0: system.cpu: ActivateContext 0
>
>  REAL SIMULATION 
>
>   0: system.kvm_vm: Mapping 1 memory region(s)
>
>   0: system.kvm_vm: Mapping region: 0x0x7f0b007b7000 -> 0x0 [size:
> 0x8]
>
>   0: system.kvm_vm: vmFD is 5, p1 is 140724538190576
>
>   0: system.cpu: charlie, vcpuID is 0
>
>   0: system.kvm_vm: vmFD is 5, p1 is 0
>
>   0: system.kvm_vm: *debug vcpuID is 0
>
> panic: KVM: Failed to create virtual CPU
>
> Memory Usage: 33838804 KBytes
>
> Program aborted at tick 0
>
> --- BEGIN LIBC BACKTRACE ---
>
> ./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x5622a4c15f8c]
>
> ./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x5622a4c30b6a]
>
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1305ea6980]
>
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1304430fb7]
>
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1304432921]
>
> ./build/X86/gem5.opt(+0x6e5cef)[0x5622a3f20cef]
>
> ./build/X86/gem5.opt(_ZN5KvmVM10createVCPUEl+0x9ff)[0x5622a4953b8f]
>
> ./build/X86/gem5.opt(_ZN10BaseKvmCPU7startupEv+0x9e)[0x5622a494bc8e]
>
> ./build/X86/gem5.opt(_ZN9X86KvmCPU7startupEv+0x9)[0x5622a4969509]
>
>
> --
>
>
>
> *发件人:* Jason Lowe-Power [mailto:ja...@lowepower.com ]
>
> *发送时间:* 2021年5月10日 23:56
> *收件人:* gem5 users mailing list 
> *抄送:* Liyichao 
> *主题:* Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch
>
>
>
> Hmm, I don't immediately know what's going wrong. I would extend the panic
> on line 559 of vm.cc to also print the error code number so you can look it
> up. I believe you can use `errno` like normal after calling `ioctl`. For
> instance, you could add `strerror(errno)` to the panic.
>
>
>
> Cheers,
>
> Jason
>
>
>
>
>
> On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi All:
>
>  I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM:
> Failed to create virtual CPU”.
>
>
>
>
>
> My host is X86 server of Intel 6148 and it can support kvm:
>
> lsmod |grep kvm
>
> kvm_intel 172032  0
>
> kvm   548864  1 kvm_

[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

2021-05-10 Thread Jason Lowe-Power via gem5-users
Hmm, I don't immediately know what's going wrong. I would extend the panic
on line 559 of vm.cc to also print the error code number so you can look it
up. I believe you can use `errno` like normal after calling `ioctl`. For
instance, you could add `strerror(errno)` to the panic.

Cheers,
Jason


On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All:
>
>  I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM:
> Failed to create virtual CPU”.
>
>
>
>
>
> My host is X86 server of Intel 6148 and it can support kvm:
>
> lsmod |grep kvm
>
> kvm_intel 172032  0
>
> kvm   548864  1 kvm_intel
>
> irqbypass  16384  1 kvm
>
>
>
> ll /dev/kvm
>
> crwxrwxrwx 1 root root 10, 232 Feb 16 20:40 /dev/kvm
>
>
>
>My GEM5 version is master(v21.0.0.0),
> ea7d012c00e857ef999b88a8ec2bde801a1f
>
>
>
>
>
> ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU
> --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB
> --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I
> 5000 -c "./test"
>
> gem5 Simulator System.  http://gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
>
>
> gem5 version 21.0.0.0
>
> gem5 compiled May 10 2021 03:39:51
>
> gem5 started May 10 2021 03:57:48
>
> gem5 executing on ubuntu, pid 112188
>
> command line: ./build/X86/gem5.opt configs/example/se.py
> --cpu-type=X86KvmCPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches
> --l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB
> --num-cpus=1 -I 5000 -c ./test
>
>
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>
> Global frequency set at 1 ticks per second
>
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (32768 Mbytes)
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
>  REAL SIMULATION 
>
> panic: KVM: Failed to create virtual CPU
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[gem5-users] Re: When using clwb “panic: Tried to write unmapped address” in Gem5 X86

2021-05-07 Thread Jason Lowe-Power via gem5-users
Hi Arun,

Two quick ideas...

1. The address 0x56318e53ed40 looks suspect. That's not on the stack, in
the OS, on the heap... I think it's probably a bad address. Most likely
some other instruction before this one is causing a bad address to be
emitted.

2. CLWB/CLFLUSH/CLFLUSHOPT may or may not be implemented in the core model
and in the memory system you're using.  I'd take a look at the Exec trace
to see exactly what microops are executing and then also trace the
cache/memory system to make sure the effects are what you expect.

Cheers,
Jason

On Mon, May 3, 2021 at 8:16 AM Arun Kavumkal via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I am running a linked list with each node having *512Bytes* allocated
> using malloc. I am then flushing cache line aligned addresses (using
> *clwb*) from this 512Bytes to measure the flush overhead. The benchmark
> works fine in Linux X86 system. But while running in gem5, I am getting the
> following error. Can someone please point me to possible issue. The gem5  I
> am using is an earlier version.
>
> Gem5 command :
>
> *gem5/build/X86/gem5.opt gem5/configs/example/se.py --cmd=$command
> --options="$options" --l1d-hwp-type=StridePrefetcher
> --l2-hwp-type=BOPPrefetcher --cpu-type=DerivO3CPU --mem-type=DDR4_2400_16x4
> --caches --l2cache --mem-size=10GB*
>
> $command and $options takes benchmark values
>
> The benchmark works fine with other flush variants, ie *clflush* and
> *clflushopt*
>
> Thanks a lot, I am trying to figure out the issue from couple of days, but
> could not yet
>
> panic: Tried to write unmapped address 0x56318e53ed40.
> PC: 0x20ee, Instr:   CLWB_M : clwb   %ctrl155, DS:[rcx]
> Memory Usage: 10697132 KBytes
> Program aborted at tick 225239086116
> --- BEGIN LIBC BACKTRACE ---
> gem5/build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x563187fada8c]
> gem5/build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x563187fbfb2a]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x128a0)[0x7f8ba9c998a0]
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f8ba8275f47]
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f8ba82778b1]
> gem5/build/X86/gem5.opt(+0x51809f)[0x5631875da09f]
> gem5/build/X86/gem5.opt(_ZN6X86ISA9PageFault6invokeEP13ThreadContextRK14RefCountingPtrI10StaticInstE+0x57d)[0x56318780562d]
> gem5/build/X86/gem5.opt(_ZN13DefaultCommitI9O3CPUImplE10commitHeadERK14RefCountingPtrI13BaseO3DynInstIS0_EEj+0x8ec)[0x563187daafac]
> gem5/build/X86/gem5.opt(_ZN13DefaultCommitI9O3CPUImplE11commitInstsEv+0x529)[0x563187dabac9]
> gem5/build/X86/gem5.opt(_ZN13DefaultCommitI9O3CPUImplE6commitEv+0xaf0)[0x563187dad180]
> gem5/build/X86/gem5.opt(_ZN13DefaultCommitI9O3CPUImplE4tickEv+0xd8)[0x563187dade48]
> gem5/build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x150)[0x563187dbdef0]
> gem5/build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0xd9)[0x563187fb5c59]
> gem5/build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0x87)[0x563187fd6097]
> gem5/build/X86/gem5.opt(_Z8simulatem+0xcba)[0x563187fd70ea]
> gem5/build/X86/gem5.opt(+0xdb6e71)[0x563187e78e71]
> gem5/build/X86/gem5.opt(+0x6226ce)[0x5631876e46ce]
>
>
>
> https://stackoverflow.com/questions/67371156/when-using-clwb-panic-tried-to-write-unmapped-address-in-gem5-x86
> ___
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[gem5-users] Re: 答复: TimingCPU's IPC

2021-04-27 Thread Jason Lowe-Power via gem5-users
Hello,

Check out the config.ini file in m5out/ and see what your CPU clock is
actually set to. I would guess that the options are not behaving the way
you expect (well, the way anyone would expect). se.py (and the options in
Options.py) is pretty fundamentally broken. There are tons of special cases
and other things that will overwrite options that you pass. There's no
guarantee when you say "--cpu-clock=2GHz" on the command line that the
CPU's clock is actually set to 2GHz. I strongly suggest using your own
configuration files like in Learning gem5.

Cheers,
Jason

On Tue, Apr 27, 2021 at 5:58 AM Liyichao via gem5-users 
wrote:

> My cmd is ./build/ARM/gem5.opt --debug-flags=Exec configs/example/se.py
> --cpu-type=TimingSimpleCPU -c "/mnt/root/stream" --caches --cpu-clock="2GHz"
>
>
>
> The Exec debug output:
>
>
>
>
>
> 3558000: system.cpu: T0 : @strlen+36:   bics   x4, x4, x5:
> IntAlu :  D=0x
>
> 83559000: system.cpu: T0 : @strlen+40:   bic   x5, x6, x7 :
> IntAlu :  D=0x808080808080
>
> 8356: system.cpu: T0 : @strlen+44:   ccmp   x5, #0, #0, eq:
> IntAlu :  D=0x
>
> 83561000: system.cpu: T0 : @strlen+48:   b.eq  :
> IntAlu :
>
> 83562000: system.cpu: T0 : @strlen+52:   csel   x4, x4, x5, cc:
> IntAlu :  D=0x8080808080808000
>
> 83563000: system.cpu: T0 : @strlen+56:   movz   x0, #8, #0:
> IntAlu :  D=0x0008
>
> 83564000: system.cpu: T0 : @strlen+60:   rev   x4, x4 :
> IntAlu :  D=0x0080808080808080
>
> 83565000: system.cpu: T0 : @strlen+64:   clz   x4, x4 :
> IntAlu :  D=0x0008
>
> 83566000: system.cpu: T0 : @strlen+68:   csel   x0, xzr, x0, cc   :
> IntAlu :  D=0x
>
> 83567000: system.cpu: T0 : @strlen+72:   add   x0, x0, x4, LSR #3 :
> IntAlu :  D=0x0001
>
>
>
> 1 instrution need 1000 ticks, it means that 1 instrution need 2 cycles,
> ipc is 0.5. Is it correct?
>
>
>
> *发件人:* Bobby Bruce [mailto:bbr...@ucdavis.edu]
> *发送时间:* 2021年4月27日 12:55
> *收件人:* gem5 users mailing list 
> *抄送:* Liyichao 
> *主题:* Re: [gem5-users] TimingCPU's IPC
>
>
>
> Could you give a bit more info about your configuration here? To be
> honest, it looks like the CPU is just running at 1GHz instead of 2. Is that
> possible?
>
>
>
> --
>
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
>
>
> web: https://www.bobbybruce.net
>
>
>
>
>
> On Fri, Apr 23, 2021 at 3:52 AM Liyichao via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi All:
>
>  As I know, Atomic or Timing CPU’s IPC is 1 IPC, but when I test a
> program in SE mode with –debug-flags=Exec, in the debug output file, I find
> that one instruction’s tick is incremented by 1000, my cpu frequency is 2
> GHz. Does that mean that the IPC is 0.5(cycle=1000/500)?
>
> Is the 1IPC is calculated under 1GHz?
>
>
>
>
>
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[gem5-users] Re: TBE Tables in Ruby and Garnet Network

2021-04-26 Thread Jason Lowe-Power via gem5-users
Hi Human,

On Sun, Apr 25, 2021 at 2:43 AM MOHAMMAD HUMAM KHAN via gem5-users <
gem5-users@gem5.org> wrote:

> Hello all,
>
> I am studying MESI Two Level Protocol in gem5 using garnet2.0 network and
> CPU2006 benchmarks. I want to know the L1 Cache MSHR entries that are
> present at any point in time and also the retransmission requests that are
> happening due to various reasons. I have some queries regarding the same
> which I am not able to get through.
>
>
>1. As far as I know TBE models MSHR in the Ruby memory system. Is
>there any way using which I can access and print the TBE Tables on the
>terminal for analysis since they are present in .sm files, I had confusion
>about them?
>
> You can use DPRINTF in SLICC. So, you can modify MESI_Two_Level-L1cache.sm
to print anything you'd like.


>
>1. Also is there any relation between the request table in the
>sequencer.cc and TBE Table or they are different things?
>
> Not really. The request table tracks the CPU requests into the memory
system. The TBE table is for the transient states in the cache controllers.

>
>1. How can I know the retransmission status of a request that is
>present in the MSHR like how many times it is retransmitted, what are
>possible reasons for retransmission, etc.?
>
>
As far as I know, there are no "retransmissions." This would be handled at
the link level by the on chip network, not at the protocol level. All Ruby
protocols assume a lossless network. There are some protocols that use
acks/nacks (mostly acks as far as I remember) and those are counted in TBEs.

Another general hint would be to use the ProtocolTrace debug flag. This is
quite illuminating. You can also use the "Ruby" debug flag to get a ton of
debug information out of Ruby.

Cheers,
Jason

>
>1.
>
> Thanks in advance for your help.
>
> Regards
> Humam Khan
> IIT Guwahati, India
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[gem5-users] Re: A puzzle about how TLB is emulated

2021-04-22 Thread Jason Lowe-Power via gem5-users
Hello,

As far as I know, TLB misses are not modeled in SE mode at all.

Cheers,
Jason

On Thu, Apr 22, 2021 at 12:50 PM Θοδωρής Τροχάτος via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason! Thanks for the info!
>
> Do you know what is happening when there is a TLB miss in SE mode?
> Is the latency of a TLB miss modeled in some way in SE?
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[gem5-users] Re: A puzzle about how TLB is emulated

2021-04-22 Thread Jason Lowe-Power via gem5-users
Hi Leon,

I believe you're correct. When there is a TLB hit, it's up to the *CPU
model* to model the latency of the TLB access. I think this implementation
was designed this way to give flexibility to the CPU models. Since the TLB
is deeply embedded in the pipeline, we wouldn't want to always have a 1
cycle latency for the TLB. On the other hand, when there is a miss (in FS
mode), the page table walker will model the correct delay.

Cheers,
Jason

On Wed, Apr 21, 2021 at 6:38 AM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> While I'm doing some research about how TLB is emulated in gem5 the other
> day, I noticed that TLB costs no ticks, which is quite unusual.
> I tried printing current tick before and after (xxx is where I set in my
> print declaration):
> (1) src/cpu/o3/lsq_impl.hh
>  void LSQ::LSQRequest::sendFragmentToTranslation(int i) {
>   xxx
>   the original function body
>   xxx
>  }
> (2) src/cpu/o3/fetch_impl.hh
>  DefaultFetch::finishTranslation(const Fault , const
> RequestPtr _req) {
>   ...
>   xxx
>   if (fault == NoFault) {
> 
> fetchedCacheLines++;
> xxx
> ...
>   }
>   ...
>   }
>
> However, in both cases, both print functions printed the same tick number
> (starting from the very beginning). Is this normal or I found the wrong
> places to implant printf's or there's some misunderstanding about my
> perspective?
>
> Here is a sample of what's left on my console:
>
> !>> TLB starts @ tick=86592000
> !>> TLB ends @ tick=86592000
> !>> TLB starts @ tick=86593000
> !>> TLB ends @ tick=86593000
> !>> TLB starts @ tick=86597000
> !>> TLB ends @ tick=86597000
>
> Any pointers would do. Thanks in advance.
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[gem5-users] Re: How to measure how many ticks a particular part of process costs?

2021-04-22 Thread Jason Lowe-Power via gem5-users
Hi Leon,

This is exactly what gem5's region of interest (ROI) markers are for. You
can use these "special instructions" as either magic instructions (using
unused opcodes in the ISA) or as memory-mapped IO (useful for KVM CPUs).
You can embed these markers in your program by calling the m5ops functions.
See http://www.gem5.org/documentation/general_docs/m5ops/ for the
documentation.

Once your program has been annotated, you can modify the gem5 runscript
file by adding "system.work_begin_exit_count = 1" or
"system.exit_on_work_items = True" (not sure if these are exactly the right
parameters) which will cause the simulation to exit when the ROI begins. At
that point, in your runscript you can programmatically choose what to do
(e.g., drop a checkpoint, reset stats, dump stats, etc.). See the parsec
run script as an example:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/configs/run_parsec.py#115

Cheers,
Jason

On Thu, Apr 22, 2021 at 7:33 AM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
> I've been wondering if there's a way to measure how many ticks a
> particular part of process costs. I usually do this by hedging code blocks
> around with printf's that contain curTick() and then observing the output.
> But other than that, perhaps a better way exists? (ticks only, ie not
> pertaining to milliseconds or any other time unit)
>
> Thanks in advance.
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[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
I *think* it's possible... At one point, I got c++ std::thread to work.
I've never tried something as complex as parsec, though.

Jason

On Fri, Apr 16, 2021 at 11:17 AM John Smith  wrote:

> Does that mean I don't have to use m5threads and just use the regular
> pthread library ?
>
> On Fri, Apr 16, 2021 at 2:13 PM Jason Lowe-Power 
> wrote:
>
>> Hi John,
>>
>> Yeah, it's something like that. We usually suggest using N + 1 cores
>> where N is the number of threads. You can always use more ;).
>>
>> As a side note, if you configure things correctly (whatever that
>> means...) I believe you can get pthreads to work. You can link to the
>> pthreads on the host and I think gem5 can correctly execute that code.
>>
>> Cheers,
>> Jason
>>
>> On Fri, Apr 16, 2021 at 10:42 AM John Smith 
>> wrote:
>>
>>> That sounds great. In the meantime I will work a bit more on the SE mode.
>>> Also do you have any inputs on the following ?
>>>
>>> m5threads: If there are 9 CPU, and the host CPU launches 9 threads, then
>>> are 8 threads launched on the remaining 8 CPUs and the 9th thread has to
>>> wait for a
>>> thread to complete to begin execution. If not then where does it run as
>>> all the 9 CPUs are currently running a thread (1 host + 8 threads).
>>>
>>> Thank you,
>>> John Smith
>>>
>>> On Fri, Apr 16, 2021 at 12:58 PM Jason Lowe-Power 
>>> wrote:
>>>
>>>> Soon! https://gem5.atlassian.net/browse/GEM5-195
>>>>
>>>> We're hopeful that in the next month or so all of this code will be
>>>> public.
>>>>
>>>> Cheers,
>>>> Jason
>>>>
>>>> On Fri, Apr 16, 2021 at 9:55 AM John Smith 
>>>> wrote:
>>>>
>>>>> Will I also be able to run the GPU model in the FS mode ?
>>>>>
>>>>> On Fri, Apr 16, 2021 at 11:39 AM Jason Lowe-Power 
>>>>> wrote:
>>>>>
>>>>>> Hi John,
>>>>>>
>>>>>> I suggest using full system mode instead of SE mode if you're running
>>>>>> a multithreaded workload. In FS mode, there's a full OS so it can handle
>>>>>> thread switching, etc. For Parsec on x86 we've created a set of resources
>>>>>> for you to get started. See
>>>>>> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/
>>>>>> for details.
>>>>>>
>>>>>> Cheers,
>>>>>> Jason
>>>>>>
>>>>>> On Fri, Apr 16, 2021 at 8:07 AM John Smith via gem5-users <
>>>>>> gem5-users@gem5.org> wrote:
>>>>>>
>>>>>>> Hi All,
>>>>>>>
>>>>>>> I am sorry for the confusion.
>>>>>>>
>>>>>>> I am looking to run a multithreaded application on a mesh of 3x3
>>>>>>> CPUs, where the benchmark spawns 9 threads and each thread runs on
>>>>>>> a single CPU (1:1). I went through the past discussions on this
>>>>>>> mailing list and saw that m5threads was needed to do this. I have some
>>>>>>> questions.
>>>>>>>
>>>>>>> (1) If there are 9 CPU, and the host CPU launches 9 threads, then
>>>>>>> are 8 threads launched on the remaining 8 CPUs and the 9th thread has to
>>>>>>> wait for a
>>>>>>> thread to complete to begin execution. If not then where does it run
>>>>>>> as all the 9 CPUs are currently running a thread (1 host + 8 threads).
>>>>>>>
>>>>>>> (2) Anthony Gutierrez said that m5threads is no longer needed. Is
>>>>>>> that correct for gem5-21 ?
>>>>>>>  (Subject: Simulating multiprogrammed & multithreaded workloads
>>>>>>> in SE mode?)
>>>>>>>
>>>>>>> (3) Right now I am trying to build PARSEC 3.0 benchmarks with
>>>>>>> m5threads, but I am receiving some errors as follows and I am not sure 
>>>>>>> why:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> *base_dir/local/gcc/bin/gcc -O3 -g -funroll-loops
>>>>>>> -fprefetch-loop-arrays  base_dir/gem5dev/parsec-3.0/pkgs/pthread.o
>>>&g

[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
Hi John,

Yeah, it's something like that. We usually suggest using N + 1 cores where
N is the number of threads. You can always use more ;).

As a side note, if you configure things correctly (whatever that means...)
I believe you can get pthreads to work. You can link to the pthreads on the
host and I think gem5 can correctly execute that code.

Cheers,
Jason

On Fri, Apr 16, 2021 at 10:42 AM John Smith  wrote:

> That sounds great. In the meantime I will work a bit more on the SE mode.
> Also do you have any inputs on the following ?
>
> m5threads: If there are 9 CPU, and the host CPU launches 9 threads, then
> are 8 threads launched on the remaining 8 CPUs and the 9th thread has to
> wait for a
> thread to complete to begin execution. If not then where does it run as
> all the 9 CPUs are currently running a thread (1 host + 8 threads).
>
> Thank you,
> John Smith
>
> On Fri, Apr 16, 2021 at 12:58 PM Jason Lowe-Power 
> wrote:
>
>> Soon! https://gem5.atlassian.net/browse/GEM5-195
>>
>> We're hopeful that in the next month or so all of this code will be
>> public.
>>
>> Cheers,
>> Jason
>>
>> On Fri, Apr 16, 2021 at 9:55 AM John Smith  wrote:
>>
>>> Will I also be able to run the GPU model in the FS mode ?
>>>
>>> On Fri, Apr 16, 2021 at 11:39 AM Jason Lowe-Power 
>>> wrote:
>>>
>>>> Hi John,
>>>>
>>>> I suggest using full system mode instead of SE mode if you're running a
>>>> multithreaded workload. In FS mode, there's a full OS so it can handle
>>>> thread switching, etc. For Parsec on x86 we've created a set of resources
>>>> for you to get started. See
>>>> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/
>>>> for details.
>>>>
>>>> Cheers,
>>>> Jason
>>>>
>>>> On Fri, Apr 16, 2021 at 8:07 AM John Smith via gem5-users <
>>>> gem5-users@gem5.org> wrote:
>>>>
>>>>> Hi All,
>>>>>
>>>>> I am sorry for the confusion.
>>>>>
>>>>> I am looking to run a multithreaded application on a mesh of 3x3 CPUs,
>>>>> where the benchmark spawns 9 threads and each thread runs on
>>>>> a single CPU (1:1). I went through the past discussions on this
>>>>> mailing list and saw that m5threads was needed to do this. I have some
>>>>> questions.
>>>>>
>>>>> (1) If there are 9 CPU, and the host CPU launches 9 threads, then are
>>>>> 8 threads launched on the remaining 8 CPUs and the 9th thread has to wait
>>>>> for a
>>>>> thread to complete to begin execution. If not then where does it run
>>>>> as all the 9 CPUs are currently running a thread (1 host + 8 threads).
>>>>>
>>>>> (2) Anthony Gutierrez said that m5threads is no longer needed. Is that
>>>>> correct for gem5-21 ?
>>>>>  (Subject: Simulating multiprogrammed & multithreaded workloads in
>>>>> SE mode?)
>>>>>
>>>>> (3) Right now I am trying to build PARSEC 3.0 benchmarks with
>>>>> m5threads, but I am receiving some errors as follows and I am not sure 
>>>>> why:
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> *base_dir/local/gcc/bin/gcc -O3 -g -funroll-loops
>>>>> -fprefetch-loop-arrays  base_dir/gem5dev/parsec-3.0/pkgs/pthread.o
>>>>> -static-libgcc -Wl,--hash-style=both -Wl,--as-needed
>>>>> -DPARSEC_VERSION=3.0-beta-20150206 -o siman_tsp siman_tsp.o  -L
>>>>> base_dir/local/gcc/lib64 -L base_dir/local/gcc/lib ./.libs/libgslsiman.a
>>>>> ../rng/.libs/libgslrng.a ../ieee-utils/.libs/libgslieeeutils.a
>>>>> ../err/.libs/libgslerr.a ../sys/.libs/libgslsys.a 
>>>>> ../utils/.libs/libutils.a
>>>>> -lpthread -lmbase_dir/gem5dev/parsec-3.0/pkgs/pthread.o: In function
>>>>> `__pthread_initialize_minimal':pthread.c:(.text+0x97): undefined reference
>>>>> to `_dl_phdr'pthread.c:(.text+0xd9): undefined reference to `_dl_phnum'*
>>>>>
>>>>> Generally how should I go about integrating the m5thread with any
>>>>> benchmark?
>>>>>
>>>>> (4) Also, what other CPU benchmarks are recommended which are
>>>>> multithreaded and can be run in a manner where I can
>>>>> launch a thread on each CPU ?
>>>>>
>>>>

[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
Soon! https://gem5.atlassian.net/browse/GEM5-195

We're hopeful that in the next month or so all of this code will be public.

Cheers,
Jason

On Fri, Apr 16, 2021 at 9:55 AM John Smith  wrote:

> Will I also be able to run the GPU model in the FS mode ?
>
> On Fri, Apr 16, 2021 at 11:39 AM Jason Lowe-Power 
> wrote:
>
>> Hi John,
>>
>> I suggest using full system mode instead of SE mode if you're running a
>> multithreaded workload. In FS mode, there's a full OS so it can handle
>> thread switching, etc. For Parsec on x86 we've created a set of resources
>> for you to get started. See
>> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/
>> for details.
>>
>> Cheers,
>> Jason
>>
>> On Fri, Apr 16, 2021 at 8:07 AM John Smith via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi All,
>>>
>>> I am sorry for the confusion.
>>>
>>> I am looking to run a multithreaded application on a mesh of 3x3 CPUs,
>>> where the benchmark spawns 9 threads and each thread runs on
>>> a single CPU (1:1). I went through the past discussions on this mailing
>>> list and saw that m5threads was needed to do this. I have some questions.
>>>
>>> (1) If there are 9 CPU, and the host CPU launches 9 threads, then are 8
>>> threads launched on the remaining 8 CPUs and the 9th thread has to wait for
>>> a
>>> thread to complete to begin execution. If not then where does it run as
>>> all the 9 CPUs are currently running a thread (1 host + 8 threads).
>>>
>>> (2) Anthony Gutierrez said that m5threads is no longer needed. Is that
>>> correct for gem5-21 ?
>>>  (Subject: Simulating multiprogrammed & multithreaded workloads in
>>> SE mode?)
>>>
>>> (3) Right now I am trying to build PARSEC 3.0 benchmarks with m5threads,
>>> but I am receiving some errors as follows and I am not sure why:
>>>
>>>
>>>
>>>
>>>
>>> *base_dir/local/gcc/bin/gcc -O3 -g -funroll-loops -fprefetch-loop-arrays
>>>  base_dir/gem5dev/parsec-3.0/pkgs/pthread.o -static-libgcc
>>> -Wl,--hash-style=both -Wl,--as-needed -DPARSEC_VERSION=3.0-beta-20150206 -o
>>> siman_tsp siman_tsp.o  -L base_dir/local/gcc/lib64 -L
>>> base_dir/local/gcc/lib ./.libs/libgslsiman.a ../rng/.libs/libgslrng.a
>>> ../ieee-utils/.libs/libgslieeeutils.a ../err/.libs/libgslerr.a
>>> ../sys/.libs/libgslsys.a ../utils/.libs/libutils.a -lpthread
>>> -lmbase_dir/gem5dev/parsec-3.0/pkgs/pthread.o: In function
>>> `__pthread_initialize_minimal':pthread.c:(.text+0x97): undefined reference
>>> to `_dl_phdr'pthread.c:(.text+0xd9): undefined reference to `_dl_phnum'*
>>>
>>> Generally how should I go about integrating the m5thread with any
>>> benchmark?
>>>
>>> (4) Also, what other CPU benchmarks are recommended which are
>>> multithreaded and can be run in a manner where I can
>>> launch a thread on each CPU ?
>>>
>>> Thank You,
>>> John Smith
>>>
>>> <https://www.mail-archive.com/search?l=gem5-users@gem5.org=from:%22Gutierrez%2C+Anthony%22>
>>>
>>> On Fri, Apr 16, 2021 at 1:50 AM Gabe Black via gem5-users <
>>> gem5-users@gem5.org> wrote:
>>>
>>>> That's essentially right, although gem5 does have some plumbing to run
>>>> multiple event queues within the same simulation which can coordinate with
>>>> each other within a small window (quantum) of time. gem5 has support for
>>>> fibers/threads/coroutines, but these are not typically used to model
>>>> events. Events are processed inline when they happen using a simple
>>>> function call.
>>>>
>>>> Gabe
>>>>
>>>> On Thu, Apr 15, 2021 at 2:46 AM gabriel.busnot--- via gem5-users <
>>>> gem5-users@gem5.org> wrote:
>>>>
>>>>> Hi John,
>>>>>
>>>>> Short answer : no, you can only run several simulations in parallel,
>>>>> but not a single simulation using one thread per CPU.
>>>>>
>>>>> Gem5 relies on Discrete Event Simulation (DES) to simulate the
>>>>> concurrent behavior of HW.
>>>>> DES is intrinsically sequential in its execution as it relies on
>>>>> coroutines (also called user user threads, greed threads, fibers, etc.).
>>>>> Parallelizing such application is a very hard task that often requires
>>>>&

[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
Hi John,

I suggest using full system mode instead of SE mode if you're running a
multithreaded workload. In FS mode, there's a full OS so it can handle
thread switching, etc. For Parsec on x86 we've created a set of resources
for you to get started. See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/
for details.

Cheers,
Jason

On Fri, Apr 16, 2021 at 8:07 AM John Smith via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> I am sorry for the confusion.
>
> I am looking to run a multithreaded application on a mesh of 3x3 CPUs,
> where the benchmark spawns 9 threads and each thread runs on
> a single CPU (1:1). I went through the past discussions on this mailing
> list and saw that m5threads was needed to do this. I have some questions.
>
> (1) If there are 9 CPU, and the host CPU launches 9 threads, then are 8
> threads launched on the remaining 8 CPUs and the 9th thread has to wait for
> a
> thread to complete to begin execution. If not then where does it run as
> all the 9 CPUs are currently running a thread (1 host + 8 threads).
>
> (2) Anthony Gutierrez said that m5threads is no longer needed. Is that
> correct for gem5-21 ?
>  (Subject: Simulating multiprogrammed & multithreaded workloads in SE
> mode?)
>
> (3) Right now I am trying to build PARSEC 3.0 benchmarks with m5threads,
> but I am receiving some errors as follows and I am not sure why:
>
>
>
>
>
> *base_dir/local/gcc/bin/gcc -O3 -g -funroll-loops -fprefetch-loop-arrays
>  base_dir/gem5dev/parsec-3.0/pkgs/pthread.o -static-libgcc
> -Wl,--hash-style=both -Wl,--as-needed -DPARSEC_VERSION=3.0-beta-20150206 -o
> siman_tsp siman_tsp.o  -L base_dir/local/gcc/lib64 -L
> base_dir/local/gcc/lib ./.libs/libgslsiman.a ../rng/.libs/libgslrng.a
> ../ieee-utils/.libs/libgslieeeutils.a ../err/.libs/libgslerr.a
> ../sys/.libs/libgslsys.a ../utils/.libs/libutils.a -lpthread
> -lmbase_dir/gem5dev/parsec-3.0/pkgs/pthread.o: In function
> `__pthread_initialize_minimal':pthread.c:(.text+0x97): undefined reference
> to `_dl_phdr'pthread.c:(.text+0xd9): undefined reference to `_dl_phnum'*
>
> Generally how should I go about integrating the m5thread with any
> benchmark?
>
> (4) Also, what other CPU benchmarks are recommended which are
> multithreaded and can be run in a manner where I can
> launch a thread on each CPU ?
>
> Thank You,
> John Smith
>
> 
>
> On Fri, Apr 16, 2021 at 1:50 AM Gabe Black via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> That's essentially right, although gem5 does have some plumbing to run
>> multiple event queues within the same simulation which can coordinate with
>> each other within a small window (quantum) of time. gem5 has support for
>> fibers/threads/coroutines, but these are not typically used to model
>> events. Events are processed inline when they happen using a simple
>> function call.
>>
>> Gabe
>>
>> On Thu, Apr 15, 2021 at 2:46 AM gabriel.busnot--- via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi John,
>>>
>>> Short answer : no, you can only run several simulations in parallel, but
>>> not a single simulation using one thread per CPU.
>>>
>>> Gem5 relies on Discrete Event Simulation (DES) to simulate the
>>> concurrent behavior of HW.
>>> DES is intrinsically sequential in its execution as it relies on
>>> coroutines (also called user user threads, greed threads, fibers, etc.).
>>> Parallelizing such application is a very hard task that often requires a
>>> lot of subtle code transformations to efficiently protect shared resources.
>>> If done correctly, then parallel DES does not have all the good
>>> properties of classic DES, especially determinism... Unless you add extra
>>> care to preserve it, which is hard, too. Trust me ;).
>>>
>>> This question has been discussed back in the days but seems stalled now:
>>> http://www.m5sim.org/Parallel_M5
>>>
>>> Cheers,
>>> Gabriel
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[gem5-users] Re: Referencing an upstream component in parameters

2021-04-14 Thread Jason Lowe-Power via gem5-users
Hi Gabriel,

I agree it's not intuitive and it's a bit awkward.

Is there a reason for adopting that design? My guess is that it allows to
> build the system top to bottom in the python scripts.
>

Haha! No, there's not an underlying reason for this. In fact, I would guess
that there is a much better design which wouldn't require this awkward
pattern. As an aside, I was recently re-writing some Ruby config scripts
and got bitten by these circular dependencies as they require you to
construct your system in a very strange way.

Cheers,
Jason

On Wed, Apr 14, 2021 at 1:36 AM gabriel.busnot--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
> Thanks for your reply, it should be an adequate solution, even if it looks
> kind of awkward to me right now ;)
> While I wanted the downstream controller (B) to have a reference to the
> upstream (proxied) controller (A), I must actually do the opposite and have
> (A) store a reference to (B).
> Then, (A).init() will call (B).registerUpstream(this).
> It does not feel natural to set this "(B) references (A)" relationship in
> (A)'s python parameters but it is required not tho create a cycle in the
> hierarchy.
>
> Looking at it again, it looks like, for instance, a RubyController
> references a RubySystem that references the System in turn.
> So the inclusion relationship in python parameters is the opposite of the
> architectural inclusion relationship, if I can say so.
> In other words, if C++ class (B) needs a reference to C++ class (A),
> Python class (A) will typically hold a reference to Python class (B) and
> (A).init() will call (B).registerA(this).
> Is there a reason for adopting that design? My guess is that it allows to
> build the system top to bottom in the python scripts.
>
> Cheers,
> Gabriel
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[gem5-users] Re: Referencing an upstream component in parameters

2021-04-13 Thread Jason Lowe-Power via gem5-users
Hi Gabriel,

First, Ruby is a bit of a mess as far as circular dependencies go. Some of
this is historic, and some of it is inherent to the design. I'm not too
surprised you're running into this issue.

The SimObject initialization is documented here:
http://doxygen.gem5.org/release/current/classSimObject.html#details

Basically, after construction (which happens in m5.instantiate()), the
init() function is called on all SimObjects (in an arbitrary order). In
that init() function, you can have an object call "registerParent" or
something like that on its child to set up the pointers between parent and
child.

Here's an example in Ruby:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/ruby/network/Network.cc#62

Note that with Ruby, since almost everything has a pointer to the
RubySystem, it's pretty easy for either the parent or the child to set up
this connection. Again, the design is a bit of a mess, but it should be
relatively straightforward to do what you're trying to do.

Cheers,
Jason

On Tue, Apr 13, 2021 at 6:36 AM gabriel.busnot--- via gem5-users <
gem5-users@gem5.org> wrote:

> I am currently hacking my way through it using the NodeID (e.g,
> (A).version on python side) as a parameter of controller (B) so that I can
> basically write in (B)'s state machine :
> MachineID proxiedController :=
> createMachineID(MachineType:, proxiedNodeID);
>
> It seems to work for now but I would like at least not to have
> MachineType: hardcoded in (B).
> Ideally, I would like to be able to get (A)'s MachineID dynamically when
> initializing (B) and use it as a constant for the rest of the simulation.
>
> I understand that it goes against the component-hierarchy-based
> implementation that instantiates components bottom up, relying on the
> absence of dependencies between a component and its parents.
> But, is there a way to perform some post-instanciation setup operations
> like with the [before_]end_of_elaboration() SystemC callbacks?
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[gem5-users] Re: Question about multi-socket simulation for x86

2021-04-12 Thread Jason Lowe-Power via gem5-users
Hi Chris,

Using Garnet or SimpleNetwork with Ruby will allow you to set the latency
of each link to anything you'd like and create any topology you'd like. You
should be able to configure this to model a multi-socket system. That said,
it's unclear if any of the current protocols will model a modern
multi-socket system.

Cheers,
Jason

On Fri, Apr 9, 2021 at 10:08 AM Chris Zhang via gem5-users <
gem5-users@gem5.org> wrote:

> Dear all,
>
> I wonder is it possible to simulate a multi-socket machine for x86. I
> think there is one such option with Arm named num-cluster
> .
> Does it exist an equivalent knob in x86?
>
> Thanks!
>
> Best,
> Chris
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[gem5-users] Re: Out of order memory responses

2021-03-30 Thread Jason Lowe-Power via gem5-users
Yes! That's no problem at all. The default memory controller is FRFCFS and
it snoops the write queue, so it is already out of order :).

Cheers,
Jason

On Tue, Mar 30, 2021 at 12:32 PM lsteiner--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
> thank's for your help. So if I have understood correctly I can change the
> request order in the memory controller and send the responses back to the
> cache in this new order.
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[gem5-users] Re: Out of order memory responses

2021-03-30 Thread Jason Lowe-Power via gem5-users
Hello,

Generally, there are no requirements or restrictions on memory access order
in gem5. In Ruby, you can create a protocol that requires the network to be
in order, but most protocols assume networks that are not explicitly
ordered. The classic caches have no ordering restrictions.

Cheers,
Jason

On Tue, Mar 30, 2021 at 6:07 AM lsteiner--- via gem5-users <
gem5-users@gem5.org> wrote:

> Anyone here that can help me?
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[gem5-users] Re: Problem with SimpleCache provided by learning_gem5/part2 when the ISA is ARM

2021-03-29 Thread Jason Lowe-Power via gem5-users
Hi Fugelin,

This is an interesting bug! I would guess that there's a packet being
copied in the cache when it should be reused. The simple cache isn't tested
with Arm, and it's really just an example and shouldn't be used for
anything "real". If you do figure out the bug, we'd love to accept your
contribution!

Cheers,
Jason

On Tue, Mar 23, 2021 at 8:48 PM Gelin Fu via gem5-users 
wrote:

> Hi all,
>
> I am a freshman about gem5, so I try the learing_gem5 tutorial first. When
> I was modeling SimpleCache in the tutorial part2, I find this model can
> only work well with X86, not ARM. The screen outputs as follows:
> gem5 version 20.1.0.4
> gem5 compiled Mar 24 2021 11:38:19
> gem5 started Mar 24 2021 11:40:55
> gem5 executing on fgl-virtual-machine, pid 46006
> command line: build/ARM/gem5.opt configs/tutorials/simple_cache.py
>
> warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
> warn: membus.master is deprecated. `master` is now called
> `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot
> file and pdf.
> warn: DRAM device capacity (8192 Mbytes) does not match the address
> range assigned (512 Mbytes)
> 0: system.remote_gdb: listening for remote gdb on port 7000
> warn: CoherentXBar system.membus has no snooping ports attached!
> Beginning simulation!
> info: Entering event queue @ 0.  Starting simulation...
> gem5.opt: build/ARM/mem/request.hh:776: uint64_t
> Request::getExtraData() const: Assertion
> `privateFlags.isSet(VALID_EXTRA_DATA)' failed.
> Program aborted at tick 12055000
>
> I would like to know if this SimpleCache object can be used for the ARM
> ISA or the reason why it cannot be used for ARM  ISA.
>
> Thanks and regards
> Fugelin
>  Xi'an Jiaotong University
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[gem5-users] Re: Error: Can't find a working Python installation

2021-03-27 Thread Jason Lowe-Power via gem5-users
What I can say confidently is that I've never been able to get a virtual
environment to work with gem5. It will 100% definitely work with python3
and scons installed on the system.

Jason

On Fri, Mar 26, 2021 at 10:18 PM haurunis--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
> Thank you for your reply.
> Does it mean for now, [gem5 build] (
> http://learning.gem5.org/book/part1/building.html#:~:text=To%20build%20gem5%2C%20we%20will,build%20directory%20when%20first%20executed.)
> has to be done with python3 & scons installed in the system, rather than
> the anaconda environment?
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[gem5-users] Re: Error: Can't find a working Python installation

2021-03-26 Thread Jason Lowe-Power via gem5-users
Hello,

> I wonder how do I make gem5 detect the python in my current anaconda env,
while I can directly run by `python`?

This is difficult, and I've really struggled to get this to work with gem5.
You need to make sure that scons picks up the correct `python3-config`
binary. It *might* work to specify the python3-config binary with
`--python-config=/python3-config`

Cheers,
Jason

On Fri, Mar 26, 2021 at 8:56 AM haurunis--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi, I am building gem5 as shown here in python==3.7, scons==4.0.1 to build
> scons. Following (http://learning.gem5.org/book/part1/building.html), but
> I ran into the error as below:
> ```
> $ scons build/X86/gem5.opt -j8
> scons: Reading SConscript files ...
> Checking for linker -Wl,--as-needed support... yes
> Checking for pkg-config package protobuf... yes
> Checking for compiler -gz support... no
> Warning: Can't enable object file debug section compression
> Checking for linker -gz support... no
> Warning: Can't enable executable debug section compression
> Info: Using Python config: python3-config
> Checking for C header file Python.h... yes
> Checking for C library python3.7m... yes
> Checking for C library crypt... yes
> Checking for C library pthread... yes
> Checking for C library dl... yes
> Checking for C library util... yes
> Checking for C library rt... yes
> Checking for C library m... yes
> Checking Python version... no
> Error: Can't find a working Python installation
> ```
> Seems like the `py_version`(
> https://github.com/gem5/gem5/blob/ea7d012c00e857ef999b88a8ec2bde801a1f/SConstruct#L560)
> stays false. I wonder how do I make gem5 detect the python in my current
> anaconda env, while I can directly run by `python`?
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[gem5-users] Some gem5 infrastructure down

2021-03-17 Thread Jason Lowe-Power via gem5-users
Hi all,

We're having an issue with the billing for our Google cloud infrastructure.
There may be intermittent issues with gem5 infrastructure for a little
while. We hope to get this resolved within a few hours.

Cheers,
Jason
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[gem5-users] Re: Simobjects in gem5

2021-03-11 Thread Jason Lowe-Power via gem5-users
It's not terribly useful, but you can list all SimObjects with `gem5.opt
--list-simobjects` (or something like that, use `gem5.opt --help` to find
the exact argument).

You can also check in the src/mem/ directory for files that end in .py.
These files are the SimObject description files and all SimObjects can be
found in similar files. Since you're interested in the memory system, say,
you'll find the memory objects in src/mem.

Cheers,
Jason

On Thu, Mar 11, 2021 at 3:40 AM 1348046572--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
> I have studied the gem5 documentation.
> But now I'm confused about how can I know what SimObjects can I use.
> Are there any documents I can look up to know all the already implemented
> SimObjects?
> For example, if I want to use the memory bus in gem5, I even don't know
> any other SimObjects'name except for SystemXBar mentioned in the
> getting-started documentation.
>
> system.membus = SystemXBar()
>
> I want to use gem5 to build a domain-specific accelerator. So I need to
> know all the SimObjects I can use in gem5.
> Thank you very much.
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[gem5-users] Re: gem5 and non volatile memory

2021-02-16 Thread Jason Lowe-Power via gem5-users
Hi Krishnan,

There is also a native NVM model in gem5 now. See
http://www.gem5.org/2020/05/27/memory-controller.html for details.

Also, though not as well integrated with gem5, there is VANS from UCSD:
https://github.com/TheNetAdmin/VANS

Cheers,
Jason

On Tue, Feb 16, 2021 at 2:51 PM Samuel Thomas via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Krishnan,
>
> In a project for class, I updated some code for NVmain so that it will at
> least run with the current commit of gem5. You can find it here:
> https://github.com/samueltphd/NVmain
>
> I haven’t touched it since the course completed, so there are probably
> some updates that can be done to it still, so feel free to take the work
> and update/modify it. :)
>
> Best,
> Sam
>
> On Feb 16, 2021, at 12:54 PM, krishnan gosakan via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi all,
> I have been using gem5 for some time and interested in experimenting with
> non volatile memory. I found a couple of github projects on gem5 and nvmain
> integrations but they are very old. I just want to check with the community
> if there are any new additions to gem5 which makes non volatile memory a
> part of the project. Would be happy to learn more about this.
> Thank you all.
> --
> Regards,
> Krishnan.
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[gem5-users] Re: run a binary file for 3 times on gem5

2021-02-01 Thread Jason Lowe-Power via gem5-users
Hello,

I don't think there's a simple way to do this in SE mode. In FS mode, you
could write a simple shell script to execute the program in a loop. One
thing you can do is to modify the program to execute the ROI multiple times.

Cheers,
Jason

On Sun, Jan 31, 2021 at 5:20 PM ABD ALRHMAN ABO ALKHEEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> How to run a binary file three times on gem5? I want to find the execution
> time for a binary file for 1M instructions. However, the gem5 is completed
> on 400K instructions because the binary file is completed. So how I can run
> it three times in order to reach 1M instructions?
>
> For example, If I want to run the hello world on gem5 using the following
> command, the gem5 will end before reach 10k insts since hello needs only 5k
> insts to finish. So ho i can run it for 3 times?
>
> build/X86/gem5.opt configs/example/se.py -I 1 -c
> tests/test-progs/hello/bin/x86/linux/hello --cpu-type=DerivO3CPU --caches
>
> Any help would be appreciated.
>
> Thanks
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[gem5-users] Re: write if-else statement in slicc transition code blocks.

2021-02-01 Thread Jason Lowe-Power via gem5-users
Hello,

If you want to trigger two different transitions based on different inputs,
this should always go in the in_port definition. For instance, see
http://www.gem5.org/documentation/learning_gem5/part3/cache-in-ports/. You
can base this on the message information by using peek() on the buffer. If
you want to trigger based on the cache state, you should make sure the
state you need is stored in the TBE or cache block as a "State". Then, the
transition tagged with that state as a starting state will be triggered.

It's best practice to never use if statements except in in_ports. Remember,
you're describing a state machine, not writing imperative code. SLICC is
more like verilog than it is C/C++.

Jason

On Sun, Jan 31, 2021 at 5:33 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone:
>   Recently, I am making some changes to the cache coherence protocol in
> Gem5, in the SLICC documents, I should add some if-else statements, but the
> transitions code blocks seem do not to cover this case, it shows syntax
> error >>if<<. If I do so, should I change the related parts like action
> code blocks and basic configurations?
> Such as:
> if (..){
> transition(..)
> }
> else{
> transition(..)
> }
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[gem5-users] Re: Gem5 hardware arrays

2021-01-25 Thread Jason Lowe-Power via gem5-users
I believe that's referring to RAM generally (e.g., registers, caches, DRAM,
etc.)

Cheers,
Jason

On Mon, Jan 11, 2021 at 10:23 PM husin alhaj ahmade via gem5-users <
gem5-users@gem5.org> wrote:

> "Gem5 already includes all key microarchitecture components which model
> hardware arrays on which faults of any duration and severity can be
> injected. [1
> ]"
>
> " hardware arrays" What does that mean?
>
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2021-01-25 Thread Jason Lowe-Power via gem5-users
Hi Zhen,

Sorry for missing your previous message.

(1) I think the biggest difference is that the former does not implement a
port for each bank, is it right?
- I guess it assumes that the banks are the bottlenecks not the ports. It
assumes that the banks are distributed and have separate ports, IIRC.

For the L1TagArrayRead... If the transition reads both the I-cache tag and
the L1 tag, then yes. I don't have a definitive answer for you. It depends
on how you want to model the performance.

Cheers,
Jason

On Sat, Jan 23, 2021 at 4:07 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
>   I have tag every transition in the cache controller (i.e.,
> MESI_Three_Level-L0cache.sm) with the required resources, but there is
> something wrong, during the
> implementation of the L0 multi-bank, I have doubt whether need to add L1
> RequestType? It also means require L1 cache resources.
> for example:
>   transition(I, Ifetch, Inst_IS) {ITagArrayRead}{
> pp_allocateICacheBlock;
> i_allocateTBE;
> a_issueGETS;
> uu_profileInstMiss;
> po_observeMiss;
> k_popMandatoryQueue;
> debugTransition1;
>   }
> Instruction fetch missed in the L0, should I add L1TagArrayRead like this:
> transition(I, Ifetch, Inst_IS) {ITagArrayRead, L1TagArrayRead}
>
> Looking forward to your reply.
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[gem5-users] Re: Adjusting gem5 CPU simulation granularity in heterogeneous memory environments?

2021-01-06 Thread Jason Lowe-Power via gem5-users
Hi Balazs,

That sounds a lot like elastic traces. See the documentation:
https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU and the
paper: https://ieeexplore.ieee.org/document/7482084.

Even if elastic traces don't work for your purpose, the code for them
should give you hints on how to get the information you need.

Cheers,
Jason

On Tue, Jan 5, 2021 at 4:40 PM Balazs Gerofi via gem5-users <
gem5-users@gem5.org> wrote:

> Dear Jason,
>
> Thank you for the reply. I would like to ask you a follow-up question on
> this topic.
> We are now considering to build a simplified simulator for which we would
> need detailed execution ticks of memory access instructions.
> We would like to log the timestamps when memory accesses are issued and
> retired. We found the information for issuing the instruction, but we are
> having some trouble finding the exact place in the gem5 code where a given
> memory access retires.
>
> Could you provide us some pointers?
> We are working with the O3_ARM_v7a_3 CPU model.
>
> Looking forward to hearing from you!
>
> Thanks and bests,
> Balazs
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[gem5-users] Re: Reset Stats from Software

2020-12-29 Thread Jason Lowe-Power via gem5-users
Hi Sam,

There's the "m5 utility" and the "m5 magic operations" for exactly what
you're describing! See util/m5 for details. There's some documentation here
http://www.gem5.org/documentation/general_docs/m5ops/ and in the code
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/m5/

Cheers,
Jason

On Tue, Dec 29, 2020 at 1:02 PM Samuel Thomas via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I’m writing because I would like to measure hardware statistics from only
> a certain part of a portion of a large piece of software to be run during a
> gem5 simulation. Is there a convention to this type of solution?
>
> In my head, I had mapped out the idea of writing a SimObject that behaves
> as an API for the software, and then the software can make such calls as if
> it were a system call. As I understand it, that would entail the
> src/sim/stat_control.hh file and then calling “schedStatEvent” from the API
> SimObject. Am I on the right track? Is there a cleaner/faster alternative?
>
> Best,
> Sam
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[gem5-users] Re: CXL protocol model simulation support schedual in GEM5

2020-12-29 Thread Jason Lowe-Power via gem5-users
Hello,

The quick answer is "no," we don't have any CXL implementation. However,
that seems like a great idea, and would be a great contribution to the
community!

I assume that you would be doing this Ruby. Feel free to let me know if you
have any questions or run into any issues.

Cheers,
Jason

On Fri, Dec 25, 2020 at 6:53 PM Liyichao via gem5-users 
wrote:

> Hi all:
>
>
>
>  We are currently studying the CXL protocol. Do you have a
> development plan for the CXL protocol simulation model in the GEM5
> community or have developers started to implement the model, including the
> driver, HOST/DEVICE module implementation, and consistency protocol?
>
>
>
>
>
> TKS!
>
>
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[gem5-users] Re: A question regarding to .sm file

2020-12-09 Thread Jason Lowe-Power via gem5-users
Hi Leon,

SLICC really is its own language. It looks like C++ only to make it simpler
to implement, not because you should be able to write C++ code. If you
haven't read the Learning gem5 Ruby section, I would suggest starting
there: http://www.gem5.org/documentation/learning_gem5/part3/MSIintro/. I
believe this video may be helpful as well:
https://www.youtube.com/watch?v=XTIrVBb86aM=youtu.be

Cheers,
Jason

On Wed, Dec 9, 2020 at 2:29 AM Leon Zhao via gem5-users 
wrote:

> Hi all,
>
> I'm currently doing some research in Ruby, therefore I've been trying to
> modify some .sm file such as
> 'src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm'. I was wondering how
> come this C++-like language cannot recognize simplest syntax such as a
> simple semicolon.
>
> Also, if I want to define a function in this file, would it be appropriate
> to just define it in another C++ file and declare the header file in
> StateMachine.py? Is there something I missed?
>
> Any pointers would do. Thank you in advance.
>
> Leon
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[gem5-users] Re: How to invoke the schedule() function in .sm file

2020-12-09 Thread Jason Lowe-Power via gem5-users
Hi Leon,

Scheduling arbitrary events is not allowed in SLICC. The SLICC language is
meant only for defining state machines and their actions. Any scheduling,
etc. should either be done within the restrictions of SLICC or outside of
SLICC in some other way. For instance, you could add a new method to the
CacheMemory object.

Another option if you need to trigger some other action from a SLICC action
would be to use a "trigger queue". This is a special message buffer which
you can enqueue your own messages and can trigger an event on an in_port in
a subsequent cycle. You can even specify a latency for the trigger queue as
well. Many SLICC protocols have examples of using a trigger queue.

Cheers,
Jason

On Wed, Dec 9, 2020 at 2:40 AM Leon Zhao via gem5-users 
wrote:

> Hi all,
>
> I noticed that in 'src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm',
> in getAccessPermission() function, a line like 'TBE tbe := TBEs[addr];'
> appeared, and I suppose it's the corresponding line of 'lookup()'. In my
> research, I want this line to be scheduled by schedule() as in many C++
> files.
>
> I tried to modify the codes with, like, 'schedule(doThis, Cycles(1))' but
> unfortunately, when I define doThis, a lambda expression is required with a
> std::function, which would trigger a syntax error of not
> recognizing lambda expression.
>
> Does anyone have idea of how to fix this problem? Much obliged!
>
> Leon
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[gem5-users] Re: X86 Elastic Trace Replay

2020-11-18 Thread Jason Lowe-Power via gem5-users
Hey Patrick,

This isn't exactly an answer to your question, but you can find a similarly
"simple" x86 FS configuration in the gem5-resources repository. E.g.,
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/
.

I'm sure that it's *possible* to do what you're suggesting and set up the
replay mechanism's system to match that of FSConfig.makeLinuxX86System.
However, it may be easier to use a different script that's not fs.py so you
can better understand how the system is being constructed.

Cheers,
Jason

On Mon, Nov 16, 2020 at 3:09 PM Patrick Sheridan (psheridan) via gem5-users
 wrote:

> Micron Confidential
>
> I am trying to replay an elastic trace taken with an X86 system (built
> similarly as in fs.py – using common.FSConfig.makeLinuxX86System).
>
>
>
> However, when I try to replay the trace, using the same system, but
> switching to the TraceCPU, I get the following assertion error:
>
>
>
> gem5.opt: build/X86/sim/system.hh:133: const System::Threads::Thread&
> System::Threads::thread(ContextID) const: Assertion `id < size()' failed.
>
>
>
> In looking at the example etrace_replay.py, I see that, by contrast, the
> system is constructed much more simply – using the System() constructor
> directly.  However, I was wondering if it is possible to make use of the
> common.FSConfig.makeLinuxX86System function (which uses makeX86System) as
> it does a lot with regard to setting up the bus hierarchy correctly.
>
>
>
> Thanks,
>
> Patrick
>
> Micron Confidential
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[gem5-users] Re: gem5 stats , LLC average miss latency

2020-11-18 Thread Jason Lowe-Power via gem5-users
Hi Arun,

That time is in simulator *ticks*, not cycles. By default, the tick time is
1ps, so that would be an average latency of 3.8us, which is high, but seems
possible for non-volatile memory.

Cheers,
Jason

On Sun, Nov 15, 2020 at 11:43 PM Arun Kavumkal via gem5-users <
gem5-users@gem5.org> wrote:

> I am running Gem5, X86, SE mode in 4 cores with CPU running at 3GHz (set
> using --cpu-clock in Options.py), L1, L2 are private and L3 is shared. I am
> using classic cache.
>
> ```
> system.l3.demand_avg_miss_latency::.cpu0.data 3861061.012024   # average
> overall miss latency
> ```
>
> I am a little confused about the ***average miss latency values***
> reported by Gem5 stats, since the value is ***3861061 cycles*** which ~
> 1.2 ms (considering 3GHz CPU clock). Isn't too high latency to access
> memory on an average considering  memory access times are always mentioned
> as 100s of CPU cycles. I am using [NVMainMemory][1] as main memory,but
> still avg access time in milliseconds does not fit in.
>
> Am I missing something here?
>
> Thanks
> Arun
>
>   [1]: https://github.com/SEAL-UCSB/NVmain
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[gem5-users] Re: Multi-process shared memory in SE mode

2020-11-03 Thread Jason Lowe-Power via gem5-users
Hi Pedro,

No, I don't have any specific pointers beyond the code in src/sim/. One
quick note: on develop there is something in flux about how syscalls work.
There's been some recent changes from Gabe to the "Workload" and the
syscall dispatch. I have to admit I don't understand them, but it might be
worth looking into before diving in.

Cheers,
Jason

On Tue, Oct 27, 2020 at 1:39 PM Pedro Becker via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason, thanks for the feedback!
>
> About your suggestions:
> - Yes, pthreads worked correctly for the simple examples I tried. But
> still has this drawback of shared memory I was trying to avoid..
> - Do you have any pointers on implementing syscalls on gem5? It could be
> anything I could take as a 'guide' to get started with it since I'm not
> sure about how hard or easy that might be. I'll take a look since it might
> be a good solution for the short-term goals of making multi-processing work.
>
> Again, thank you.
>
> Best,
> Pedro.
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-11-03 Thread Jason Lowe-Power via gem5-users
Hello,

(1) Yes, I believe so.
(2) I thought MOESI_hammer was annotated, but it doesn't look like
(huh...). However, AMD MOESI Base is annotated. See all of the transition
in the core-pair file, for instance:
https://gem5.googlesource.com/public/gem5/+/refs/tags/v20.1.0.0/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm#2480

Cheers,
Jason

On Thu, Oct 29, 2020 at 5:54 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> (1) Can I use resource stalls to simulate the multi-bank implementation of
> L0 and L1, and  model L2 a distributed cache? By the way, the
> implementation of L2 multi-bank in gem5 is not interleaving (multi-bank),
> right?
> (2) "add annotations to the transitions in the L0 and L1 cache", I am not
> sure how this should be done, could you give me an example?
>
> Looking forward to your reply.
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[gem5-users] Re: What is the role of TimeBuffer in gem5?

2020-11-03 Thread Jason Lowe-Power via gem5-users
Hello,

I've been using gem5 for ~10 years, and this is the first time I've ever
seen this code :D. It  was committed 14 years ago, and it hasn't been
touched since.

It looks to me like it's used for gathering statistics about the activity
of different CPU pipeline stages. However, I *know* it's not actively
maintained, so I would guess that it doesn't work anymore. As far as what
it's doing, I think the comment in activity.hh is probably the best
explanation:

http://doxygen.gem5.org/release/current/classActivityRecorder.html#details

Cheers,
Jason

On Tue, Nov 3, 2020 at 4:49 AM yujiecui--- via gem5-users <
gem5-users@gem5.org> wrote:

> What does TimeBuffer in gem5 do? I read its source code, but there are no
> comments and it is not easy to understand operations. I saw in the tick
> function in the cpu.cc file that every tick() will proceed
> timeBuffer.advance();
> fetchQueue.advance();
> decodeQueue.advance();
> renameQueue.advance();
> iewQueue.advance();
> But the function of advance is
> advance()
> {
>  if (++base >= size)
> base = 0;
> int ptr = base + future;
> if (ptr >= (int)size)
> ptr -= size;
> (reinterpret_cast(index[ptr]))->~T();
> std::memset(index[ptr], 0, sizeof(T));
> new (index[ptr]) T;
> }
> Just looking at the source code, this is really hard to understand. I
> think if someone can tell me what it is doing? I think it’s easier for me
> to understand this code
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-28 Thread Jason Lowe-Power via gem5-users
Hello,

For (1), yes. You can set this *in the python configuration file*. You
should not modify the SimObject description file to change a default
parameter.

For (2), yes, that's exactly where you should modify.

Cheers,
Jason

On Wed, Oct 28, 2020 at 9:47 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> I would use the resource stalls to model banking, I have read
> src/mem/ruby/structures/Rubycache.py and
> src/mem/ruby/structures/BankedArray.cc
> (1)  I have seen
> dataArrayBanks = Param.Int(1, "Number of banks for the data array")
> tagArrayBanks = Param.Int(1, "Number of banks for the tag array")
>
> If I want to configure multiple banks, can I directly modify these
> parameters?
>
> (2) To extend the BankedCache implementation to model arbitrary address
> interleaving, which files or functions should I modify?
> Should I modify the following function in
> src/mem/ruby/structures/BankedArray.cc?
> unsigned int
> BankedArray::mapIndexToBank(int64_t idx)
> {
> if (banks == 1) {
> return 0;
> }
> return idx % banks;
> }
>
> Looking forward to your reply.
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[gem5-users] Re: Multi-level TLB is implemented in performance

2020-10-28 Thread Jason Lowe-Power via gem5-users
Yes, this is possible, and I believe it's already implemented for Arm.

The best place to start is src/arch//tlb.cc

Cheers,
Jason

On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,all. I would like to know if it is possible to implement multi-level
> TLB on gem5 performance by modeling the latency of TLB. If so, which files
> or functions should I start with?
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[gem5-users] Re: Multi-process shared memory in SE mode

2020-10-27 Thread Jason Lowe-Power via gem5-users
Hi Predro,

It would certainly be easier in FS mode :D. Also, I would worry that the
system call emulation layer might not model your application with high
enough fidelity if you care about multithreaded apps (e.g., the futex
system call will take 0 time in SE mode).

If you dynamically link your application to the pthread library, it
*should* work, at least functionally, in SE mode. This has been tested in
the past. However, I don't think we have a test for it in our current
regressions, so it's possible this has been broken.

If using different processes in SE mode is a requirement, I think the only
option is to implement the shared memory syscalls. If you go this route, we
would be happy to take the contribution of these new syscall
implementations upstream!

Cheers,
Jason

On Tue, Oct 27, 2020 at 2:15 AM Pedro Becker via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> Is it possible to do any form of communication between two applications
> running in SE mode?
>
> I know we can span two apps with the se.py script with -c "app1;app2", but
> if one of these apps try to use syscalls like shmget() or shmat()
> simulation does not work because the syscalls are not implemented.
> I could simulate the communication between threads (with pthreads), but
> I'd like to do it with different processes (with separate memory spaces).
>
> Is there any way do to it? Am I obligated to use the FS mode in this case?
>
> Thank you.
>
> ---
> Pedro Becker.
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[gem5-users] Re: How to run Python code with TensorFlow in Gem5 syscall emulation mode?

2020-10-23 Thread Jason Lowe-Power via gem5-users
Hi Hasan,

I agree with Abhishek. Something as complex as tensorflow is going to be
very difficult to get working in syscall emulation mode. Using full system
mode should work (though without things like GPU acceleration, of course).

Cheers,
Jason

On Fri, Oct 23, 2020 at 1:55 PM Abhishek Singh via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Hasan,
> I have been trying to run tensorflow on gem5, have you tried full system?
> I was able to run simple python code like hello on it.
> Let me know if it works
>
> On Fri, Oct 23, 2020 at 12:28 PM Hasan, S M Shamimul via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hello,
>>
>> * I want to run cosmoGAN code inside Gem5. The cosmoGAN code is available
>> here (https://github.com/MustafaMustafa/cosmoGAN). The cosmoGAN code is
>> in Python language, which uses TensorFlow. To run some code inside the
>> Gem5, I need a binary file of my code. Hence, how can I run cosmoGAN Python
>> code in the Gem5 syscall emulation mode?
>>
>> * Earlier, I was interested to know how I can run a simple "Hello World"
>> code in Gem5 syscall emulation mode. Therefore, I posted the following
>> question in StackOverflow.
>>
>> StackOverflow Question Link:
>> ===
>>
>> https://stackoverflow.com/questions/6344/is-it-possible-to-run-python-code-in-gem5-syscall-emulation-mode
>>
>> In the StackOverflow answer, Ciro Santilli told me to implement syscalls.
>> I was getting an error for the "fchmod" syscall. Hence, I implemented it in
>> the following file (/gem5/src/arch/x86/linux/process.cc) like below.
>> However, it was not working for me. The Gem5 creates a large output file,
>> and after that, it terminates.
>>
>> Syscall Implementation:
>> ==
>> { 91, "fchmod", fchmodFunc },
>>
>> * Please let me know how I can run cosmoGAN Python code (with TensorFlow)
>> in the Gem5 syscall emulation mode?
>>
>> Thank you in advance.
>>
>> Sincerely,
>> S.M.Shamimul Hasan
>>
>>
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> --
> Best Regards,
> Abhishek
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-21 Thread Jason Lowe-Power via gem5-users
In this case, I would use the resource stalls to model banking. You can
extend the BankedCache implementation to model arbitrary address
interleaving, if that's important to your model. To do this, you'll have to
add annotations to the transitions in the L0 and L1 cache, but this should
be easier than implementing "real" banking.

Cheers,
Jason

On Wed, Oct 21, 2020 at 8:20 AM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> I want to configure L0 and L1 as Multi-Banking (Interleaving) Caches ,
> considering  L0 and L1 are private, so I have two questions:
> (1). If L0 and L1 are configured as multiple banks, do I need to connect
> L0 to the ruby ​​network?
>
> (2). To configure multiple banks, should I need to add a cache controller
> for each bank?
>
> Looking forward to your reply.
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[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-21 Thread Jason Lowe-Power via gem5-users
Honestly, I'm not sure. I would need to dig much deeper into the
MESI_Three_Level protocol to be able to help.

Jason

On Tue, Oct 20, 2020 at 9:06 PM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> In MOESI_hammer, the state transition in the I state is defined as follows,
>
> transition({I, IR}, Flush_line, IM_F) {
> it_allocateTBE;
> bf_issueGETF;
> k_popMandatoryQueue;
>   }
>
> So I wonder if it should be defined like this in MESI_Three_Level, or
> simply handle flush and keep the I state unchanged?
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[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-20 Thread Jason Lowe-Power via gem5-users
I would look to see how it's done in MOESI_hammer.

https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/ruby/protocol/MOESI_hammer-cache.sm#902

Cheers,
Jason

On Tue, Oct 20, 2020 at 9:04 AM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> It is really difficult to add flush in the MESI protocol. If I need to
> switch from the timing mode to KVM multiple times, do I have to add
> operations that support flush to the MESI protocol?
>
> By the way, for the cache block in the I state, it only needs to be
> processed simply when it encounters flush. But I don't know how to define
> the action more appropriately?
> action(flushResponse)
> {sequencer.flushResponse(); }
>
> void Sequencer::flushResponse(Addr address, DataBlock)
> {
> writecallback(address, data);
> }
>
> ___
> The flushResponse I defined only has writecallback, I think this is not
> appropriate, but I don’t know what else needs to be added, do you think
> anything else needs to be added?
> Looking forward to your reply.
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[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-20 Thread Jason Lowe-Power via gem5-users
Hello,

The lack of error when writing a checkpoint doesn't mean it was successful.
Likely, the data was not written back to memory correctly if the random
test is failing.

No, you cannot use `writeCallbackScFail`. This is to signal that a store
conditional has failed.

It might help to learn about Ruby and SLICC more generally. I wrote a large
section of Learning gem5 about ruby here:
http://www.gem5.org/documentation/learning_gem5/part3/MSIintro/

In general, modifying SLICC protocols is difficult and error prone. Unlike
a lot of other programming, you can't just change random things and hope
that it works. You really need to have a protocol designed on paper before
diving into implementation.

Another useful thing is the html output from SLICC. When you compile with
scons, if you add SLICC_HTML=True you will get an html rendering of the
protocol, which can be helpful for "on paper" debugging.

Cheers,
Jason

On Mon, Oct 19, 2020 at 8:09 PM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> I defined the following transitions when flushing is executed in the I
> state, I did not use ruby_random_test.py to test at first, but created
> checkpoint in SE mode, and no error was reported, printed information shows
> flush_line I->I.
> But when I execute the following command line, use ruby_random_test.py to
> test, and modify the script to test flush, when this transition(I,
> Flush_line) is executed, it stops.
>
> Command:
> --debug-flags=ProtocolTrace ./configs/example/ruby_random_test.py -n 4
> --ruby
>
> transition(I, Flush_line) {
> flushRespsonse;
> }
>
> action(flushResponse) {
> sequencer.writeCallbackScFail(address, cache_entry.DataBlk);
> }
> writeCallbackScFail is on the sequencer
> void
> Sequencer::writeCallbackScFail(Addr address, DataBlock& data)
> {
> llscClearMonitor(address);
> writeCallback(address, data);
> }
> __
> I don't know why this error reported in Ruby random tester, Is it because
> I can't use writeCallbackScFail as the flush response when block is in I?
> If so, how can the  flush be handled more appropriately?
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[gem5-users] Re: Any one bootup with fs.py in gem5 version 20.1 with dramsim3 or nvmain succuessfully

2020-10-20 Thread Jason Lowe-Power via gem5-users
Hello,

DRAMSim isn't a drop in replacement for the memory object anymore. Since
the change in the memory interface (
http://www.gem5.org/project/2020/10/01/gem5-20-1.html#new-dram-interface-contributed-by-wendy-elsasser)
you can't just drop in a different type of DRAM model.

You'll probably have to modify fs.py, Options.py, or something like that to
be able to use DRAMSim3. There are already some special cases for
"SimpleMemory" and you should be able to copy that for DRAMSim3.

Cheers,
Jason

On Mon, Oct 19, 2020 at 9:00 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  I use gem5 20.1 ,and bootup with fs.py and dramsim3 model,but
> some error printed.
>
>
>
>  As I know, gem5 20.1 new feature has departed the medium
> interface from memctrl, however, these modifications are only for the DRAM
> model inside gem5, I think external memory Dramsim3 and NVmain do not adapt
> to these changes.
>
>
>
>
>
> my script:
> ./build/ARM/gem5.opt --debug-flags=DRAM -d ./m5out configs/example/fs.py
> --cpu-type=O3_ARM_v7a_3 --kernel=vmlinux -n 2
> --machine-type=VExpress_GEM5_V1
> --disk-image=aarch64-ubuntu-trusty-headless.img --bootloader
> ./system/arm/bootloader/arm64/boot.arm64 --caches --l2cache
> --checkpoint-dir=./m5out --mem-type=DRAMsim3 --mem-size=2GB
>
> Error:
> Traceback (most recent call last):
> File "", line 1, in 
> File "build/ARM/python/m5/main.py", line 457, in main
> exec(filecode, scope)
> File "configs/example/fs.py", line 339, in 
> test_sys = build_test_system(np)
> File "configs/example/fs.py", line 234, in build_test_system
> MemConfig.config_mem(options, test_sys)
> File "/home/l30005758/upstream/configs/common/MemConfig.py", line 237, in
> config_mem
> mem_ctrl.dram = dram_intf
> File "build/ARM/python/m5/SimObject.py", line 1337, in _setattr_
> value = param.convert(value)
> File "build/ARM/python/m5/params.py", line 215, in convert
> return self.ptype(value)
> TypeError: _init_() takes 1 positional argument but 2 were given
> Error setting param MemCtrl.dram to 
> --
>
> 李翼超(Charlie)
>
>
>
> 华为技术有限公司 Huawei Technologies Co., Ltd.
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-19 Thread Jason Lowe-Power via gem5-users
Hello,

It depends on how you want to model banking. If you just want to set and
limit the bandwidth to a cache, you can use the "resourceStalls = true"
option on the RubyCache object and set the tag and data array values. You
will also have to tag every transition in the cache controller (i.e.,
MESI_Two_Level-L2cache.sm) with the required resources (see MOESI_hammer
for an example).

If you want to model a distributed cache, then you can configure your "L2"
caches to have a slice of the address range and update the
"mapAddressToRange" function to map the addresses to the correct
distributed caches. This could be as simple as setting the
l2_select_num_bits parameter on the "L1" caches.

Cheers,
Jason

On Wed, Oct 14, 2020 at 7:15 PM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> I want to implement multi-bank cache in ruby ​​mode, and I use the
> MESI_Three_Level protocol to maintain the consistency of the three-level
> cache. Which scripts should I modify to realize multi-bank cache ?
>
> (1) Do I need to modify all the .sm files in src/mem/ruby/protocol/,  such
> as,  MESI_Three_Level-L0cache.sm , L1cache.sm
> To Modify variables such as out_msg.Dest in the above script ?
>
> (2) Or the implementation of multi-bank cache is independent of the
> protocol and should not be modified in the above script ?
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[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-19 Thread Jason Lowe-Power via gem5-users
Hello,

It's difficult for me to say for certain without digging much deeper.
However, my gut says the latter is probably closer to correct. I doubt that
you can drop the line without first receiving an ack (somehow).

I'm not sure if this was said before, but you can use the Ruby random
tester in conjunction with the "test flushes" option to test what you're
working on. If you pass the tester with a few million loads, various sizes
of caches, etc. there is at least some confidence your implementation works
:).

Cheers,
Jason

On Fri, Oct 16, 2020 at 5:46 PM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> For  L0 cache in the MESI_Three_Level protocol, the cache block is
> initially in the M state, I considered two ways of state transition, which
> one do you think is more reasonable ?
> (1) In this case, the M state of L0 is directly changed to the I state,
> and the data is directly sent to L1;
>
>   transition(M, Flush_line, I) {
> forward_eviction_to_cpu;
> f_sendDataToL1;
> ff_deallocateCacheBlock;
> k_popMandatoryQueue;
> }
> -
> (2)In this case, the M state of L0 first becomes the MI_F intermediate
> state, and the PUTF request is sent to L1.  when L0 receiving the InvElse
> responded by L1, it is converted to the I state;
>
>   transition(M, Flush_line, MI_F) {
> i_allocateTBE;
> hh_flush_hit;
> gf_issuePUTF;
> forward_eviction_to_cpu;
> ff_deallocateCacheBlock;
> k_popMandatoryQueue;
>   }
>
>   transition({MI_F}, InvElse, I) {
> f_sendDataToL1;
> s_deallocateTBE;
> o_popIncomingResponseQueue;
> }
> --
> I don’t know which design above is more reasonable? Looking forward to
> your reply.
> ___
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[gem5-users] Re: X86KvmCPU fails -- reason code 0x80000021

2020-10-16 Thread Jason Lowe-Power via gem5-users
That's good to know, thanks, Ryan!

Is there any reason not to merge this? I know it's not a "perfect"
solution, but it would be nice if people didn't keep running into this
issue.

Bobby, can you test on both Intel and AMD (let me know if you need access
to an Intel machine). If it works, can you rebase 12278 as shown above and
let's get this submitted :D.

Cheers,
Jason

On Thu, Oct 15, 2020 at 11:20 PM Gambord, Ryan 
wrote:

> Thanks Gabe! That worked.
>
> diff --git a/src/arch/x86/fs_workload.cc b/src/arch/x86/fs_workload.cc
> index 3f46eba..f895cb6 100644
> --- a/src/arch/x86/fs_workload.cc
> +++ b/src/arch/x86/fs_workload.cc
> @@ -189,6 +189,12 @@ FsWorkload::initState()
>
>  // 32 bit data segment
>  SegDescriptor dsDesc = initDesc;
> +dsDesc.type.e = 0;
> +dsDesc.type.w = 1;
> +dsDesc.d = 1;
> +dsDesc.baseHigh = 0;
> +dsDesc.baseLow = 0;
> +
>  uint64_t dsDescVal = dsDesc;
>  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (), 8);
>
> @@ -204,10 +210,16 @@ FsWorkload::initState()
>  tc->setMiscReg(MISCREG_SS, (RegVal)ds);
>
>  tc->setMiscReg(MISCREG_TSL, 0);
> +SegAttr ldtAttr = 0;
> +ldtAttr.unusable = 1;
> +tc->setMiscReg(MISCREG_TSL_ATTR, ldtAttr);
>  tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
>  tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
>
>  SegDescriptor tssDesc = initDesc;
> +tssDesc.type = 0xB;
> +tssDesc.s = 0;
> +
>  uint64_t tssDescVal = tssDesc;
>  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (), 8);
>
>
> Ryan Gambord
> 
>
>
>
> On Thu, Oct 15, 2020 at 9:32 PM Gabe Black  wrote:
>
>> [This email originated from outside of OSU. Use caution with links and
>> attachments.]
>> As far as I know those patches should no longer be necessary, although I
>> haven't tried to run KVM on x86 recently. Other problems could be that KVM
>> isn't enabled in your BIOS or your operating system, or that the
>> permissions on the device file gem5 needs to start a VM isn't set properly.
>> Unfortunately the error you get back the hardware when *something* is wrong
>> is very generic, so it's hard to tell what it's upset about. That looks
>> like an actual code from the hardware, so I'm assuming at least the
>> permissions are set correctly.
>>
>> Between the two sets of patches, the later (12278) is definitely the one
>> you'd want. The guts of arch/x86/system.cc have moved to
>> arch/x86/fs_workload.cc, and it should be pretty easy to make equivalent
>> changes there since the actual text of the code is nearly the same.
>>
>> Gabe
>>
>> On Thu, Oct 15, 2020 at 5:42 PM Gambord, Ryan 
>> wrote:
>>
>>> Ayaz,
>>>
>>> As far as I know, those patches were superseded by this one:
>>>
>>> https://gem5-review.googlesource.com/c/public/gem5/+/12278
>>>
>>> src/arch/x86/system.cc was deleted in master, and I can find bits of the
>>> patch scattered around different files, so it kind of looks like it's been
>>> applied already? Maybe Bobby/Gabe/Jason know more about the current status
>>> of the fix?
>>>
>>> Ryan
>>>
>>>
>>> Ryan Gambord
>>> 
>>>
>>>
>>>
>>> On Thu, Oct 15, 2020 at 5:31 PM Ayaz Akram  wrote:
>>>
>>>> [This email originated from outside of OSU. Use caution with links and
>>>> attachments.]
>>>> Hello Ryan,
>>>>
>>>> I think, if you are using an Intel machine, you will still need to
>>>> apply those patches. The conversation on this issue might be useful for 
>>>> you:
>>>>
>>>> https://github.com/darchr/gem5art-experiments/issues/60
>>>>
>>>> -Ayaz
>>>>
>>>> On Thu, Oct 15, 2020 at 5:20 PM Gambord, Ryan via gem5-users <
>>>> gem5-users@gem5.org> wrote:
>>>>
>>>>> Hello all,
>>>>>
>>>>> I'm working off commit b1b8af04439240c532d3530a02773b75b9853f77
>>>>>
>>>>> I get the following error when I try to run a full-system
>>>>> (configs/example/fs.py) with the X86KvmCPU:
>>>>>
>>>>> panic: KVM: Failed to enter virtualized mode (hw reason: 0x8021)
>>>>>
>>>>> I used to have kvm working with a pre-2018 version of gem5 on this
>>>>> server, so I know it should be possible. There were a few patches floating
>>>>> around that I had to apply, but they seem to have been merged by 

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-14 Thread Jason Lowe-Power via gem5-users
Hello,

If the block is already in I, then there shouldn't be anything to
flush/write back. You should be able to simply do something like

transition(I, Flush_line) {
flushRespsonse;
}

action(flushResponse) {
sequencer.flushResponse(); (or whatever this function is on the sequencer)
}

Cheers,
Jason

On Wed, Oct 14, 2020 at 2:15 AM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> The flush event is to writeback dirty cacheline to the memory. For  L0
> cache in the MESI_Three_Level protocol, if the cache block is initially in
> the I(Invalid)state, whether this cache block need to undergo the following
> state transitions ?
> transition(I, Flush_line, IM_F)
> transition(IM_F, Data_Exclusive, M_F)
> My doubt is that the cache block in L0 is in an invalid state, whether it
> need to receive exclusive data ,i.e. transition(IM_F, Data_Exclusive, M_F)
> in the process of completing flush under the three-level cache?
> ___
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[gem5-users] Re: Invalid RubyRequestType

2020-10-12 Thread Jason Lowe-Power via gem5-users
Hi Teo,

That error is because you're still using MESI_Two_Level. You need to
recompile gem5 to use a different protocol.

I.e., to use MESI_Two_Level you could do the following:
> scons build/X86_MESI_Two_Level/gem5.opt
> build/X86_MESI_Two_Level/gem5.opt  

To use MOESI_hammer you could do the following:
> scons build/X86_MOESI_hammer/gem5.opt --default=X86 PROTOCOL=MOESI_hammer
> build/X86_MOESI_hammer/gem5.opt 

In the second case, the parameters to scons mean the following:
- `--default=X86`: Use the file build_opts/X86 to get the default
parameters for the build
- `PROTOCOL=MOESI_hammer`: Override the "PROTOCOL" variable with
MOESI_hammer

Hopefully this helps!

Cheers,
Jason


On Sun, Oct 11, 2020 at 12:28 PM Θοδωρής Τροχάτος via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all! I am new to the gem5 community and I am currently reproducing
> various things from InvisiSpec paper...
>
> I was wondering, how can I generate checkpoints in X86_MESI_Two_Level (I
> am using ruby memory model in my simulations) ?
> I know that checkpoints in Ruby can only be generated in MOESI_hammer, but
> I can't generate checkpoints with MOESI_hammer, either.
> I always get the error *"panic: Runtime Error at
> MESI_Two_Level-L1cache.sm:279: Invalid RubyRequestType."*
>
> Any ideas?
>
> Thanks in advance,
> Teo.
>
> --
> -
> *Τροχάτος Θεόδωρος*
> *Σχολή Ηλεκτρολόγων Μηχανικών & Μηχανικών Υπολογιστών*
> *Εθνικό Μετσόβιο Πολυτεχνείο*
> -
> ___
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[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-09 Thread Jason Lowe-Power via gem5-users
Hello,

It's hard for me to know what's wrong. Debugging protocols is hard! It
looks like you're moving in the right direction, though. Other than giving
you encouragement, I'm not sure I can help much.

Cheers,
Jason

On Thu, Oct 8, 2020 at 7:58 PM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> I further debugged and found that the error was reported because of the
> action( u_writeDataToCache;) in this transition;
>
>  transition({IM_F}, Data_Exclusive, M_F) {
> u_writeDataToCache;
> s_deallocateTBE;
> o_popIncomingResponseQueue;
> kd_wakeUpDependents;
> }
>   transition({IM,SM}, Data_Exclusive, M) {
> u_writeDataToCache;
> hhx_store_hit;
> s_deallocateTBE;
> o_popIncomingResponseQueue;
> kd_wakeUpDependents;
>   }
>   action(u_writeDataToCache, "u", desc="Write data to cache") {
> peek(messgeBuffer_in, CoherenceMsg) {
>   assert(is_valid(cache_entry));
>   cache_entry.DataBlk := in_msg.DataBlk;
> }
>   }
> Program stops here, assert(is_valid(cache_entry)),Below is the code
> corresponding to L0 Cache_Controller.cc,
>
> ---
> /** \brief Write data to cache */
> void
> L0Cache_Controller::u_writeDataToCache(L0Cache_TBE*& m_tbe_ptr,
> L0Cache_Entry*& m_cache_entry_ptr, Addr addr)
> {
> DPRINTF(RubyGenerated, "executing u_writeDataToCache\n");
> try {
>{
> // Declare message
> const CoherenceMsg* in_msg_ptr M5_VAR_USED;
> in_msg_ptr = dynamic_cast *>(((*m_bufferFromL1_ptr)).peek());
> if (in_msg_ptr == NULL) {
> // If the cast fails, this is the wrong inport (wrong message
> type).
> // Throw an exception, and the caller will decide to either try a
> // different inport or punt.
> throw RejectException();
> }
> (*m_cache_entry_ptr).m_DataBlk = ((*in_msg_ptr)).m_DataBlk;
> }
>
> } catch (const RejectException & e) {
>fatal("Error in action L0Cache:u_writeDataToCache: "
>  "executed a peek statement with the wrong message "
>  "type specified. ");
> }
> }
>
> 
> The transition({IM_F}, Data_Exclusive, M_F) defined by me refers to the
> existing transition({IM,SM}, Data_Exclusive, M) in the MESI_Three_Level
> protocol,So I don’t know why an error occurs when executing
> action(u_writeDataToCache) in the transition defined by myself?
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[gem5-users] Re: CPU configuration and default values

2020-10-08 Thread Jason Lowe-Power via gem5-users
Hi Davide,

I echo 100% of what Giacomo said. Also, there's a proposal for updating the
Python API here: https://gem5.atlassian.net/browse/GEM5-432. That proposal
is a pretty extreme example, and we'll probably end up with something
closer to the status quo.

You can also check out Learning gem5 to understand more about how to write
config scripts from scratch:
https://www.gem5.org/documentation/learning_gem5/part1/simple_config/.

Finally, if you're interested in x86 FS scripts, there are some examples in
gem5 resources (e.g.,
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/configs/system/
).

Cheers,
Jason

On Thu, Oct 8, 2020 at 3:04 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Davide,
>
>
>
> You are 100% right in your distinction between example platforms
> (forkable) and generic scripts; and that no-one should ever fork from
> fs.py; and that such script, if we still want to maintain it, shouldn’t be
> in the example directory. The “simple example script to replicate to match
> your use case” is the de-facto accepted philosophy among most gem5
> developers (nowadays). The idea is to empower a user/researcher to easily
> adjust a python config to model a specific hardware topology.
>
>
>
> Some people in Arm got that in mind when they added the
> configs/example/arm subdir:
>
> https://github.com/gem5/gem5/tree/stable/configs/example/arm
>
>
>
> About investing some of your own time on cleaning up the configs: that
> would be great and I feel most maintainers are already sharing your views
> on what needs to be changed.
>
> If you are afraid of not having your patch accepted on upstream, a
> solution could be for you to post a RFC using JIRA (
> https://gem5.atlassian.net/secure/BrowseProjects.jspa)
>
> where you could describe what will be restructured and how. You will get a
> feedback from the rest of the community and you could make the decision
> whether it’s worth investing some of your time.
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
> *From:* Davide Basilio Bartolini 
> *Sent:* 08 October 2020 10:40
> *To:* gem5 users mailing list 
> *Cc:* Giacomo Travaglini 
> *Subject:* Re: CPU configuration and default values
>
>
>
> Hi Giacomo,
>
>
>
> Thanks for your reply, I'll take a closer look at fs_bigLITTLE.py.
>
>
>
> I guess the question here for the gem5 maintainers is whether gem5 users
> are expected to hack their own simulation script even for "simple" cases or
> if there should be default scripts that don't have this kind of
> idiosyncrasies with default parameters (and possibly other legacy).
>
> Probably, the current answer is "yes", given that se.py and fs.py are in
> an "examples" directory.
>
> That doesn't seem ideal to me though: generic scripts to parse parameters
> and run simulations look like "standard" infrastructure to me that the
> simulator should probably provide, rather than examples that users are
> expected to fork and hack on (except for specific / advanced case).
>
>
>
> I guess the question there is whether the community wants to go in that
> direction or not.
>
> If yes, then thinking about promoting those "examples" to a more stable
> status and refactoring legacy issues along the way might be a good thing to
> think about.
>
> I (or others) could spend some time working on that, but it really only
> makes sense if there is a chance that the patch will be eventually accepted
> upstream, otherwise it's just simpler to have our own scripts on the
> side (as most people probably do already).
>
>
>
> Thanks.
>
>
>
> -- dbb
>
>
> --
>
> *From:* Giacomo Travaglini via gem5-users 
> *Sent:* Thursday, October 8, 2020 11:17:43 AM
> *To:* gem5 users mailing list
> *Cc:* Davide Basilio Bartolini; Giacomo Travaglini
> *Subject:* [gem5-users] Re: CPU configuration and default values
>
>
>
> Hi Davide,
>
>
>
> This is annoying indeed. The main problem IMHO is that you shouldn’t be
> using Options.py in the first place (this is why I am not personally using
> swiss army knife scripts like fs.py).
>
> I suggest you to have a look at fs_bigLITTLE.py and use that as a
> reference for a main/top level python config.
>
>
>
> Having said that, this is actually a real problem for people still using
> fs.py-like scripts. Unfortunately removing default values from Options.py
> will likely break some legacy scripts for some users, so I don’t feel
> comfortable on doing it myself. It would be nice if at a certain point we
> would take the brave decision of removing the script.
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> *From:* Davide Basilio Bartolini via gem5-users 
> *Sent:* 08 October 2020 08:02
> *To:* gem5 users mailing list 
> *Cc:* Davide Basilio Bartolini 
> *Subject:* [gem5-users] CPU configuration and default values
>
>
>
> Hi gem5 users,
>
>
>
> I am working with my team to set up a CPU model and I am having some
> trouble making sense of how the core settings are handled.
>
>
>
> The core configurations 

[gem5-users] Re: some questions while using kvm

2020-10-08 Thread Jason Lowe-Power via gem5-users
Hi Yifan,

To use the MMIO version of the m5 utility, you simply need to pass the
--addr parameter (if I remember correctly). Running `m5 --help` should
explain the options.

Cheers,
Jason

On Thu, Oct 8, 2020 at 4:14 AM  wrote:

> Hi Jason,
>
> Thank you for your quick reply. I'll check out the latest release. BTW,
> could you let me know how to use he MMIO/address version of the m5ops?
> I make the m5term in util/term.
>
> --
> Best regards,
>
> Yifan Song
>
> -原始邮件-
> *发件人:*"Jason Lowe-Power" 
> *发送时间:*2020-10-08 04:55:56 (星期四)
> *收件人:* "gem5 users mailing list" 
> *抄送:* syf1...@mail.ustc.edu.cn
> *主题:* Re: [gem5-users] some questions while using kvm
>
> Hi Yifan,
>
> First of all, the branch that you referred to is pretty old. I would use
> gem5-20.1. You can check out the gem5-resources for information on how to
> get KVM+x86 working with SPEC, Parsec, and other benchmarks.
>
> http://www.gem5.org/documentation/general_docs/gem5_resources/
>
> Switching CPUs *should* work, but it's not tested robustly for x86, so
> there could be some problems.
>
> For #3: when using KVM you must use the MMIO/address version of the m5ops.
> Since it's *real hardware* that's executing the workload, any illegal
> instructions (like the fake m5op magic instructions) will cause exceptions.
>
> Cheers,
> Jason
>
> On Tue, Oct 6, 2020 at 8:02 PM syf1997--- via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi all,
>>
>> I am using kvm to fast forward and make a checkpoint. My gem5 version is
>> https://github.com/darchr/gem5/tree/jason/kvm-testing-again
>> and I use configs/myconfigs/runkvm.py to run my simulation in FS mode
>> with custom disk-image and vmlinux-4.8.19 kernel. Here is my command line:
>> build/X86/gem5.opt --outdir=output/graph/base/1
>> configs/myconfigs/runkvm.py --disk=/home/songyifan/gem5kvm/disk/graph.img.
>> I have a couple of questions:
>> 1. The stats of simulation time (both host time and simulated time ) is
>> different though using the same command line above and configurations.
>> Sometimes the host time is close to native host machine time (about 26s)
>> and the gem5 output only contains a few warning like:
>> warn: ds: S flag not set warn: ds: P flag not set
>> and m5 terminal showed the booting is normal. On the one hand, sometimes
>> the host time is long (about 150 min) and the gem5 keeps outputting the
>> warning. I also checked the m5 terminal which showed:
>> -bash: cannot set terminal process group (1041): Inappropriate ioctl for
>> device
>> -bash: no job control in this shell
>> Also, both can run my application correctly.
>>
>> 2. When I switch my CPU from kvm to O3, I always see the outputs below in
>> m5 terminal:
>>
>> Ubuntu 16.04.6 LTS localhost.localdomain ttyS0
>>
>> localhost login: root (automatic login)
>>
>> Got CPU type: M5 Simulator
>> Welcome to Ubuntu 16.04.6 LTS (GNU/Linux 4.9.189 x86_64)
>>
>>  * Documentation:  https://help.ubuntu.com
>>  * Management: https://landscape.canonical.com
>>  * Support:https://ubuntu.com/advantage
>>
>> The programs included with the Ubuntu system are free software;
>> the exact distribution terms for each program are described in the
>> individual files in /usr/share/doc/*/copyright.
>>
>> Ubuntu comes with ABSOLUTELY NO WARRANTY, to the extent permitted by
>> applicable law.
>>
>> -bash: cannot set terminal process group (1041): Inappropriate ioctl for
>> device
>> -bash: no job control in this shell
>> 12 13
>> 12 14
>> 12 15
>> 12 16
>> read ending!!!
>> 41652231 1468365178
>> 1
>> 0 0.100
>> 1 1.2112147
>> 2
>> 1 1.2112147
>> BUG: unable to handle kernel paging request at 81035f80
>> IP: [] do_page_fault+0x0/0x1f
>> PGD 180b067 PUD 180c063
>> PMD 1e1
>> Oops: 0010 [#1] SMP
>> Modules linked in:
>> CPU: 1 PID: 1118 Comm: gem5init Not tainted 4.9.189 #1
>> Hardware name:  , BIOS  06/08/2008
>> task: 8804ed412880 task.stack: c9000117c000
>> RIP: 0010:[]  []
>> do_page_fault+0x0/0x1f
>> RSP: :c9000117ff50  EFLAGS: 002e
>> RAX: 7f66d448e2c8 RBX: 7f66d4ea49d8 RCX: 007f
>> RDX: 03f3 RSI: 0004 RDI: c9000117ff58
>> RBP: 0003 R08:  R09: 0007
>> R10: 7f66d4ca1720 R11: 022a R12: 0005
>> R13:  R14: 7f66d4ea4f50 R15: 
>> FS:  7f66d4ea2700() GS:88

[gem5-users] Re: some questions while using kvm

2020-10-07 Thread Jason Lowe-Power via gem5-users
Hi Yifan,

First of all, the branch that you referred to is pretty old. I would use
gem5-20.1. You can check out the gem5-resources for information on how to
get KVM+x86 working with SPEC, Parsec, and other benchmarks.

http://www.gem5.org/documentation/general_docs/gem5_resources/

Switching CPUs *should* work, but it's not tested robustly for x86, so
there could be some problems.

For #3: when using KVM you must use the MMIO/address version of the m5ops.
Since it's *real hardware* that's executing the workload, any illegal
instructions (like the fake m5op magic instructions) will cause exceptions.

Cheers,
Jason

On Tue, Oct 6, 2020 at 8:02 PM syf1997--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I am using kvm to fast forward and make a checkpoint. My gem5 version is
> https://github.com/darchr/gem5/tree/jason/kvm-testing-again
> and I use configs/myconfigs/runkvm.py to run my simulation in FS mode with
> custom disk-image and vmlinux-4.8.19 kernel. Here is my command line:
> build/X86/gem5.opt --outdir=output/graph/base/1
> configs/myconfigs/runkvm.py --disk=/home/songyifan/gem5kvm/disk/graph.img.
> I have a couple of questions:
> 1. The stats of simulation time (both host time and simulated time ) is
> different though using the same command line above and configurations.
> Sometimes the host time is close to native host machine time (about 26s)
> and the gem5 output only contains a few warning like:
> warn: ds: S flag not set warn: ds: P flag not set
> and m5 terminal showed the booting is normal. On the one hand, sometimes
> the host time is long (about 150 min) and the gem5 keeps outputting the
> warning. I also checked the m5 terminal which showed:
> -bash: cannot set terminal process group (1041): Inappropriate ioctl for
> device
> -bash: no job control in this shell
> Also, both can run my application correctly.
>
> 2. When I switch my CPU from kvm to O3, I always see the outputs below in
> m5 terminal:
>
> Ubuntu 16.04.6 LTS localhost.localdomain ttyS0
>
> localhost login: root (automatic login)
>
> Got CPU type: M5 Simulator
> Welcome to Ubuntu 16.04.6 LTS (GNU/Linux 4.9.189 x86_64)
>
>  * Documentation:  https://help.ubuntu.com
>  * Management: https://landscape.canonical.com
>  * Support:https://ubuntu.com/advantage
>
> The programs included with the Ubuntu system are free software;
> the exact distribution terms for each program are described in the
> individual files in /usr/share/doc/*/copyright.
>
> Ubuntu comes with ABSOLUTELY NO WARRANTY, to the extent permitted by
> applicable law.
>
> -bash: cannot set terminal process group (1041): Inappropriate ioctl for
> device
> -bash: no job control in this shell
> 12 13
> 12 14
> 12 15
> 12 16
> read ending!!!
> 41652231 1468365178
> 1
> 0 0.100
> 1 1.2112147
> 2
> 1 1.2112147
> BUG: unable to handle kernel paging request at 81035f80
> IP: [] do_page_fault+0x0/0x1f
> PGD 180b067 PUD 180c063
> PMD 1e1
> Oops: 0010 [#1] SMP
> Modules linked in:
> CPU: 1 PID: 1118 Comm: gem5init Not tainted 4.9.189 #1
> Hardware name:  , BIOS  06/08/2008
> task: 8804ed412880 task.stack: c9000117c000
> RIP: 0010:[]  [] do_page_fault+0x0/0x1f
> RSP: :c9000117ff50  EFLAGS: 002e
> RAX: 7f66d448e2c8 RBX: 7f66d4ea49d8 RCX: 007f
> RDX: 03f3 RSI: 0004 RDI: c9000117ff58
> RBP: 0003 R08:  R09: 0007
> R10: 7f66d4ca1720 R11: 022a R12: 0005
> R13:  R14: 7f66d4ea4f50 R15: 
> FS:  7f66d4ea2700() GS:8804ffd0()
> knlGS:
> CS:  0010 DS:  ES:  CR0: 80050033
> CR2: 81035f80 CR3: 000106f5e000 CR4: 0630
> Stack:
>  81435c08  7f66d4ea4f50 
>  0005 0003 7f66d4ea49d8 022a
>  7f66d4ca1720 0007  7f66d448e2c8
> Call Trace:
>  [] ? page_fault+0x28/0x30
> Code: 00 48 83 c4 30 5b 5d 41 5c 41 5d 41 5e 41 5f c3 31 d2 48 be ff ff ff
> ff ff e8 ff ff 48 bf 00 00 00 00 00 c9 ff ff e9 57 e5 ff ff <55> 48 89 f5
> 53 48 89 fb 0f 20 d0 66 66 66 90 48 89 ee 48 89 df
> RIP  [] do_page_fault+0x0/0x1f
>  RSP 
> CR2: 81035f80
> ---[ end trace 3f6da64006abaee6 ]---
> /sbin/gem5init: line 43:  1118 Killed  chmod 755
> /tmp/script
> BUG: unable to handle kernel paging request at 81035f80
> IP: [] do_page_fault+0x0/0x1f
> PGD 180b067 PUD 180c063
> PMD 1e1
> Oops: 0010 [#2] SMP
> Modules linked in:
> CPU: 1 PID: 1119 Comm: gem5init Tainted: G  D 4.9.189 #1
> Hardware name:  , BIOS  06/08/2008
> task: 880106f5e8c0 task.stack: c9000117c000
> RIP: 0010:[]  [] do_page_fault+0x0/0x1f
> RSP: :c9000117ff50  EFLAGS: 002e
> RAX: 7f66d4858220 RBX: 7f66d4ea44f0 RCX: 0001
> RDX: 001b RSI: 0004 RDI: 

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

2020-10-06 Thread Jason Lowe-Power via gem5-users
Hi Daecheol,

The complication comes from handling all of the corner cases. What happens
if you get a flush for a line when you've sent a request but haven't
received a response? What about when you've received an invalidation, but
you haven't responded yet? There are many intermediate states that you have
to reason about what the right action is in each case on a flush. It's not
*hard* it just isn't trivial.

Ignoring the flushes at the CPU may be OK. It depends on if they are
functionally required or not.

Cheers,
Jason

On Tue, Oct 6, 2020 at 1:14 AM Daecheol You  wrote:

> Thanks Jason,
>
> I just thought that FLUSH request can be handled with invalidate and
> write-back. Could you let me know what other things should be considered
> for FLUSH?  Or is it fine modifying the CPU sequencer that it just ignore
> the FLUSH request?
>
> 2020년 10월 6일 (화) 오전 8:15, Jason Lowe-Power 님이 작성:
>
>> Hi Daecheol,
>>
>> Unfortunately, the flush command is a bit more complicated to implement
>> than just a simple replacement. I responded to another message about this
>> on the mailing list a few minutes ago that you can see for more information.
>>
>> Cheers,
>> Jason
>>
>> On Mon, Sep 28, 2020 at 8:59 PM Daecheol You via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi all,
>>>
>>> I am running PARSEC benchmark with full system simulation.
>>> The CPU model is O3CPU (parameters tuned) with ARM ISA and
>>> MESI_Three_Level protocol were used. (build/ARM_MESI_Three_Level/gem5.opt)
>>> While the benchmark is running, panic occurs since the L0 cache controller
>>> gets unsupported type of request with the following message.
>>>
>>> panic: Runtime Error at MESI_Three_Level-L0cache.sm:287: Invalid
>>> RubyRequestType.
>>>
>>> I checked the type of request which triggers panic by inserting debug
>>> message at mandatory_request_type_to_event() in
>>> MESI_Three_Level-L0cache.sm. It was FLUSH request, and it is not handled
>>> properly by the protocol. It seems that other protocols also do not handle
>>> FLUSH request. I wonder why the protocol does not process FLUSH request
>>> from a mandatory queue, and how I workaround this issue.
>>>
>>> I modified the MESI_Three_Level-L0cache.sm so that it triggers
>>> L0_Replacement event and pop the mandatory queue explicitly for the FLUSH
>>> request. However, panic occurs at wakeup() function of sequencer
>>> (src/mem/ruby/system/Sequencer.cc) since the FLUSH request is not erased
>>> from the m_RequestTable. (Unlike read/writeCallback, evictionCallback does
>>> not erase the entry in request table.)
>>> It would be very helpful if you guys provide me a guide for this issue.
>>>
>>> Thanks,
>>>
>>> Daecheol.
>>> ___
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>>> To unsubscribe send an email to gem5-users-le...@gem5.org
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>>
>>
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[gem5-users] Re: Regarding ruby prefetcher requestIssued and requestCompleted bitset

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Kavya,

This looks like a bug! The RubyPrefetcher has never been regularly tested,
as far as I know. I would guess the place where these were updated got
deleted at some point and no one noticed. I'd try checking out a gem5 from
5 years ago and see if it's there. We would welcome a contribution fixing
this issue!

Cheers,
Jason

On Fri, Sep 25, 2020 at 10:48 AM Kavya Radhakrishnan via gem5-users <
gem5-users@gem5.org> wrote:

>
> In the ruby prefetcher, requestIssued and requestCompleted bitsets are
> present to track the prefetch requests that are issued and completed. Where
> are these bits getting set and reset? These are only referenced by the
> observeMiss() function.
> --
> Thanks and regards,
> Kavya
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[gem5-users] Re: Adjusting gem5 CPU simulation granularity in heterogeneous memory environments?

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Balazs,

What you suggest sounds like a panacea! I'm not sure it's possible, though
:(.

There are multiple different levels of fidelity between the O3 CPU and the
Timing Simple CPU. You could imagine other CPU models with more or less
fidelity as well, but currently these are the two main models we have
implemented.

The KVM CPU does use the hardware to execute the instructions, but there's
no way to get an address trace out of it (that I know of). You may be able
to use some cleverness with Intel's PEBS to get a trace of L1 load misses,
but I doubt that's enough detail for you. Also, this sounds very
complicated.

My favorite option (personally) is sampled simulation. However, developing
a strong sampling methodology is difficult, and there's no "out of the box"
support in gem5 (yet).

That said, your use case is an important one, and something that we would
like to be able to support. Ideas/contributions would be appreciated!

Cheers,
Jason

On Mon, Sep 28, 2020 at 10:07 PM Balazs Gerofi via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 developers/users,
>
> In order to study memory management techniques in heterogenous memory
> environments we have been working on extending gem5 to handle multiple
> memory devices (i.e., NUMA). We would like to decrease the time spent on
> simulating CPU internals without losing accuracy on memory behavior.
>
> Is there any way to simplify the simulation of processing units, e.g., is
> there a way to simply execute instructions on the host CPU but retain clock
> accuracy in the simulation of the memory subsystem?
>
> Thanks and best regards,
> Balazs
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[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Daecheol,

Unfortunately, the flush command is a bit more complicated to implement
than just a simple replacement. I responded to another message about this
on the mailing list a few minutes ago that you can see for more information.

Cheers,
Jason

On Mon, Sep 28, 2020 at 8:59 PM Daecheol You via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I am running PARSEC benchmark with full system simulation.
> The CPU model is O3CPU (parameters tuned) with ARM ISA and
> MESI_Three_Level protocol were used. (build/ARM_MESI_Three_Level/gem5.opt)
> While the benchmark is running, panic occurs since the L0 cache controller
> gets unsupported type of request with the following message.
>
> panic: Runtime Error at MESI_Three_Level-L0cache.sm:287: Invalid
> RubyRequestType.
>
> I checked the type of request which triggers panic by inserting debug
> message at mandatory_request_type_to_event() in
> MESI_Three_Level-L0cache.sm. It was FLUSH request, and it is not handled
> properly by the protocol. It seems that other protocols also do not handle
> FLUSH request. I wonder why the protocol does not process FLUSH request
> from a mandatory queue, and how I workaround this issue.
>
> I modified the MESI_Three_Level-L0cache.sm so that it triggers
> L0_Replacement event and pop the mandatory queue explicitly for the FLUSH
> request. However, panic occurs at wakeup() function of sequencer
> (src/mem/ruby/system/Sequencer.cc) since the FLUSH request is not erased
> from the m_RequestTable. (Unlike read/writeCallback, evictionCallback does
> not erase the entry in request table.)
> It would be very helpful if you guys provide me a guide for this issue.
>
> Thanks,
>
> Daecheol.
> ___
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[gem5-users] Re: How to initialize the the Stats:Scalar value and convert it to unsigned value

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Shougang,

I think you can use .value() to get the actual value out of the stat.
That should be easy to cast to an unsigned, if needed.

However, I think there might be some confusion on how to register/use the
stats. If you've registered it correctly and it is updated during
simulation (e.g., stat++ is executed) then it should be non-zero at the
end. *Importantly* you cannot access the stats directly from C++. You must
call "stats.prepare()" in python before they are ready to be processed. If
you want all of the details, you can see the file
`src/python/m5/stats/__init__.py` These details are supposed to be hidden,
and they could change at any moment. If you simply want a  counter, I
suggest using the `Counter` type.

Cheers,
Jason

On Tue, Sep 22, 2020 at 7:06 PM Shougang Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi, All,
>
> I am trying to use gem5 internal scalar data type(Stats:Scalar), I tried
> to initialize it to a fixed value and register it in the regStats()
> function, but after the simulation, I found the value dumped out is 0.
>
> And also, if I want to do some calculation based on this value and convert
> it into unsigned value, there are errors in compilation. So how can I
> convert it to unsigned value?
>
> Thanks for the help.
>
> Best regards.
>
> Shougang
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[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hello,

Yeah, adding flush to a protocol is a pretty large task, but it shouldn't
be too difficult. The key difficulty will be testing it, but the Ruby
tester does support testing flushes (probably not out of the box with
ruby_random_test.py, though).

There's no particular reason except that we haven't had the time/resources
to implement this. If you have any specific questions, I would be happy to
try to answer them.

Cheers
Jason

On Fri, Sep 25, 2020 at 7:26 AM 1154063264--- via gem5-users <
gem5-users@gem5.org> wrote:

> In Ruby System, it is only supported flush by MOESI_hammer coherence
> protocol, flush
> isn’t supported by MESI_*. This means that some protocols cannot be used
> when
> checkpointing or switching from detailed to less detailed timing modes.
>
> How can add flush in MESI_Three_Level protocol?  as I know, adding flush
> is hard. There
> are many states and events that need to be considered to support flush in
> the protocol,
> are there any good ideas to add flush to the protocol? It takes
> fundamentally updating the
> coherence protocol,
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[gem5-users] A quick note for the gem5 community

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi everyone,

We are sending this email to be as transparent as possible. The gem5
community is respectful and inclusive of all people, and we enforce these
standards in all community spaces. We as members, contributors, and leaders
pledge to make participation in our community a harassment-free experience
for everyone. See the code of conduct for details:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/CODE-OF-CONDUCT.md
.

The PMC was recently notified of a potential code of conduct violation. We
reviewed this complaint and came to the conclusion that we should not
enforce our code of conduct outside of gem5's community spaces (e.g.,
GitHub or Stack Overflow).

Instances of abusive, harassing, or otherwise unacceptable behavior may be
reported to the project management committee (PMC). The point of contact
for code of conduct violations is David Wood (da...@cs.wisc.edu) or any
other member of the PMC. See the MAINTAINERS file for a list of the current
PMC members and email addresses. All complaints will be reviewed and
investigated promptly and fairly.

Sincerely,
The gem5 PMC
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[gem5-users] Re: Segmentation fault in gem5,

2020-10-02 Thread Jason Lowe-Power via gem5-users
Hi Tao,

Thank you for bringing this to our attention. I will discuss this with the
other leaders of the community.

Have a good weekend,

Jason


On Fri, Oct 2, 2020, 6:15 PM Tao Zhang  wrote:

> Hi Jason,
>
> Thanks a lot for posting the code of conduct.
>
> Being polite is indeed important and respect should be from both sides.
>
> I couldn't see Ciro's avatar in this email thread. However, if you search
> online, go to his github/stackoverflow profile page, or even browse your
> own homepage, you would see the avatar. Below is a snapshot from your
> homepage. I believe this is what the user 1154063264 referred to.
>
> Such an avatar is inappropriate and insulting. It definitely violates the
> code of conduct.
>
> Gem5 community is a place for academic and technical discussions. It
> should not be abused to express personal political opinions. Let's work
> together to keep it away from it.
>
> Hope you all have a good weekend.
>
> Thanks,
>
> [image: Screen Shot 2020-10-02 at 5.41.55 PM.png]
>
>
> -Tao
>
>
> On Fri, Oct 2, 2020 at 10:26 AM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi everyone,
>>
>> A few things:
>> 1. Being polite is important! We strive to make the gem5 community
>> inclusive and welcoming. :)
>> 2. Email can be very impersonal. Adding a greeting and a signature with
>> your name helps create a more welcoming environment!
>> 3. When asking questions on the mailing list, help us help you. You can
>> search the issues (
>> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues) to see
>> if anything similar has been
>> reported. If you can't find any similar issues, we welcome your question,
>> but it's most helpful when we can reproduce the problem :).
>> 4. The gem5 project has a code of conduct (
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/CODE-OF-CONDUCT.md).
>> Specifically it says our standards include "Demonstrating empathy and
>> kindness toward other people" and "Being respectful of differing opinions,
>> viewpoints, and experiences." This document also details how to report a
>> violation of the community code of conduct.
>>
>> I hope everyone has a great weekend!
>>
>> Cheers,
>> Jason
>>
>> On Fri, Oct 2, 2020 at 1:25 AM Ciro Santilli via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Can you provide the URL at which the avatar you refer to is showing?
>>>
>>> On Fri, Oct 2, 2020 at 6:55 AM 1154063264--- via gem5-users
>>>  wrote:
>>> >
>>> > First of all, I thank him for answering my question. However, as a
>>> Chinese, his profile picture does not respect our country. If my behavior
>>> affects other members of the community, I am sorry.
>>> > ___
>>> > gem5-users mailing list -- gem5-users@gem5.org
>>> > To unsubscribe send an email to gem5-users-le...@gem5.org
>>> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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>
>
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[gem5-users] Re: Segmentation fault in gem5,

2020-10-02 Thread Jason Lowe-Power via gem5-users
Hi everyone,

A few things:
1. Being polite is important! We strive to make the gem5 community
inclusive and welcoming. :)
2. Email can be very impersonal. Adding a greeting and a signature with
your name helps create a more welcoming environment!
3. When asking questions on the mailing list, help us help you. You can
search the issues (
https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues) to see if
anything similar has been
reported. If you can't find any similar issues, we welcome your question,
but it's most helpful when we can reproduce the problem :).
4. The gem5 project has a code of conduct (
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/CODE-OF-CONDUCT.md).
Specifically it says our standards include "Demonstrating empathy and
kindness toward other people" and "Being respectful of differing opinions,
viewpoints, and experiences." This document also details how to report a
violation of the community code of conduct.

I hope everyone has a great weekend!

Cheers,
Jason

On Fri, Oct 2, 2020 at 1:25 AM Ciro Santilli via gem5-users <
gem5-users@gem5.org> wrote:

> Can you provide the URL at which the avatar you refer to is showing?
>
> On Fri, Oct 2, 2020 at 6:55 AM 1154063264--- via gem5-users
>  wrote:
> >
> > First of all, I thank him for answering my question. However, as a
> Chinese, his profile picture does not respect our country. If my behavior
> affects other members of the community, I am sorry.
> > ___
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