[gem5-users] sentInt() must only be used for interrupts 32 and higher
Hi all, When I was attempting to enable 2-core SMT on gem5 20.0.0.3, I encountered a panic directly caused by src/dev/arm/gic_v2.cc GicV2::sendInt(uint32_t num): /___ panic: panic condition num < SGI_MAX + PPI_MAX occurred: sentInt() must only be used for interrupts 32 and higher \ I debugged the process and confirmed that `num` was 11 at this point which is less than SGI_MAX (16) + PPI_MAX (16), i.e. 11 < 32. Correspondingly, I tried to locate the responsible device, and this appeared on my console: /___ deviceID=28945 (0x7111) \ which, I later found out, is the deviceID of IdeController in src/dev/storage/Ide.py I don't have a single clue what I'm gonna do right now, or maybe, SMT has been enabled by some other branch I don't know about? Any pointers would do. Thanks in advance! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A puzzle about how TLB is emulated
Hi Jason & Nathanael, Thank you for both of your informative replies. These have been really helpful. Leon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A puzzle about how TLB is emulated
Hi Jason, Thank you for such elaborate explanation. I will look into it. Another weird thing happened today. I noticed that while running a benchmark, TLB seemed to have never triggered a miss condition. I came to this conclusion because TLB always started and ended at the same tick according to my console (my printfs' doing), even for the first few entries since real simulation. Does this seem natural to you? Should I, in your view, run the benchmark much longer and then, like, redirect the output into a file to analyze the tick difference? Or maybe I misoperated something? Looking forward to your reply! Leon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] How to measure how many ticks a particular part of process costs?
Hi all, I've been wondering if there's a way to measure how many ticks a particular part of process costs. I usually do this by hedging code blocks around with printf's that contain curTick() and then observing the output. But other than that, perhaps a better way exists? (ticks only, ie not pertaining to milliseconds or any other time unit) Thanks in advance. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] A puzzle about how TLB is emulated
Hi all,
While I'm doing some research about how TLB is emulated in gem5 the other day,
I noticed that TLB costs no ticks, which is quite unusual.
I tried printing current tick before and after (xxx is where I set in my print
declaration):
(1) src/cpu/o3/lsq_impl.hh
void LSQ::LSQRequest::sendFragmentToTranslation(int i) {
xxx
the original function body
xxx
}
(2) src/cpu/o3/fetch_impl.hh
DefaultFetch::finishTranslation(const Fault , const RequestPtr
_req) {
...
xxx
if (fault == NoFault) {
fetchedCacheLines++;
xxx
...
}
...
}
However, in both cases, both print functions printed the same tick number
(starting from the very beginning). Is this normal or I found the wrong places
to implant printf's or there's some misunderstanding about my perspective?
Here is a sample of what's left on my console:
!>> TLB starts @ tick=86592000
!>> TLB ends @ tick=86592000
!>> TLB starts @ tick=86593000
!>> TLB ends @ tick=86593000
!>> TLB starts @ tick=86597000
!>> TLB ends @ tick=86597000
Any pointers would do. Thanks in advance.
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[gem5-users] Re: A question regarding to .sm file
Hi Jason, Thanks for replying to both questions I put forward. I'll look into it. Leon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] How to invoke the schedule() function in .sm file
Hi all, I noticed that in 'src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm', in getAccessPermission() function, a line like 'TBE tbe := TBEs[addr];' appeared, and I suppose it's the corresponding line of 'lookup()'. In my research, I want this line to be scheduled by schedule() as in many C++ files. I tried to modify the codes with, like, 'schedule(doThis, Cycles(1))' but unfortunately, when I define doThis, a lambda expression is required with a std::function, which would trigger a syntax error of not recognizing lambda expression. Does anyone have idea of how to fix this problem? Much obliged! Leon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] A question regarding to .sm file
Hi all, I'm currently doing some research in Ruby, therefore I've been trying to modify some .sm file such as 'src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm'. I was wondering how come this C++-like language cannot recognize simplest syntax such as a simple semicolon. Also, if I want to define a function in this file, would it be appropriate to just define it in another C++ file and declare the header file in StateMachine.py? Is there something I missed? Any pointers would do. Thank you in advance. Leon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A question regarding to VIPT/PIPT
Hi Ayaz, Sorry to bother you again, but the aforementioned approach that you proposed to model a VIPT in gem5 has struck me lately, since implementing a real VIPT is, now I see, not worth the fight. Any chance you could elaborate on your earlier proposition? Like, what latency I can change and how, or how to calculate the latency. Looking forward to your reply. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A question regarding to VIPT/PIPT
Hi Ayaz, Thank you so much for your instructions and I will look into it. By the way, if you have any more information on implementing VIPT in gem5, please let me know! Thanks again for your help. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A question regarding to VIPT/PIPT
Hi Ayaz, Thank you for your reply. In spite of your proposal, I still hope to implement real VIPT in gem5 (20.0.0.3). If I'm to do that, do you know what files I should modify or add and maybe something important to notice? Looking forward to your reply! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A question regarding to VIPT/PIPT
Hi Ayaz, I can't thank you enough for you reply. I'm aware of the fact that from software's perspective, VIPT and PIPT should be functioning equally but what piqued my interest is what it looks like from hardware's perspective. Let's say both i-cache and d-cache are working under PIPT, do you have any idea about what I should do if I want to implement VIPT in gem5, hopefully with no aliasing problem? Any pointers would do. Also, I scrutinized the page you mentioned above, but sadly there's no arch/arm/kernel/setup.c in my gem5 directory. Thank you again and looking forward to your reply! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] A question regarding to VIPT/PIPT
Hi everyone, I was running the following command in gem5 the other day: ..gem5.opt configs/example/fs.py --ruby --cpu-type=O3_ARM_N1 --script=tests/test-progs/hello/bin/arm/linux/hello --kernel=/home/hippo/full_system_images/binaries/vmlinux.vexpress_gem5_v1.20170616 and I noticed this appeared in the output: [0.00] CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=14c5387d [0.00] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache So when it says "PIPT / VIPT nonaliasing data cache", does it mean that on the level of data cache, there are two different routes (a) PIPT and (b) VIPT with no aliasing, or are they basically the same thing just with a difference in names? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
