>> #include at the top of addr_range_map.hh.
>> See https://gem5.googlesource.com/public/gem5/+/master/CONTRIBUTING.md
>> for more details.
>> On Tue, Jun 19, 2018 at 10:44 AM Tariq Azmy
I got a fresh new gem5 from google repo (
https://gem5.googlesource.com/public/gem5) and built the X86 with scons.
But there's an error from xbar:
In file included from build/X86/mem/xbar.hh:57:0,
Is there a way to access the data size of operand/destination register of
some instruction? For example, in mediaOpReg, there are uint8_t srcSize, as
well as uint8_t destSize but I believe these information don't get passed
to the super class, i.e. StaticInst, when it get constructed.
How is a particular instruction being decoded, especially when it has
micro-ops? I looked at the stats in commit_impl.hh
if (!inst->isMicroop() || inst->isLastMicroop())
Does this means the micro ops is also stored as a Dynamic Inst, with
> On Fri, May 25, 2018 at 2:12 PM Tariq Azmy
>> Hi Gabe, Jason,
>> Are those x86 SIMD SSE arithmetic instructions take only one cycle as
>> latency? I looked into the FuncUnitConfig.py and seems like the op lats for
>> the SIMD functional
a +1 or a +2 would be appropriate.
> On Wed, May 23, 2018 at 5:56 PM Tariq Azmy <tariqslaye...@gmail.com>
>> Thanks Gabe. Yeah it does not impact the program but it's just that the
>> statistic is incorrect.
>> By the way,
rinting a warning, but the fact that they don't actually do any math
>> isn't impacting your program for whatever reason. I'll take a quick look.
>> On Wed, May 23, 2018 at 2:07 PM, Tariq Azmy <tariqslaye...@gmail.com>
I wrote simple code that does simple floating point multiplication and
division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in
Some of cpu source codes include header files that begin with enum/.. such
Where are these sources located so that I can see 'em?
gem5-users mailing list
There is a wiki page that describes how to run PARSEC benchmark on gem5,
but it is built to run in FS mode. I wonder if anyone has tried running
those benchmarks in SE mode?
gem5-users mailing list
By "resources", I assume you are referring to each of the stage in the
out-of-order pipeline? Those stages' implementation codes (fetch, decode,
rename, etc..) are located inside the cpu/o3 directory. Branch prediction
typically is done in fetch stage, so if you look inside the fetch.hh source
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